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Last modification

  • Rev 4, 2015-05-21 17:45:25 GMT
  • Author: dgisselq
  • Log message:
    FIXED: in the previous version, the first read of the device would always fail.
    This was due to the fact that the Xilinx loader that read from the device
    to load the Xilinx configuration left the Quad SPI flash chip in a high
    data rate state. Thus, on reset, the first thing this core does it to
    take the device out of the high data rate state.

    Also, on a bus action waiting on a write to complete, the timing was
    off. This has now been corrected. Reads (in both modes) should now
    stall the bus (properly) while a write/erase cycle is ongoing, and
    complete when finished.

    The bug in high speed writing was traced to a read bug, not a write bug.
    High speed (i.e. 4-bit transaction) writing has been re-enabled.

    The bug in transitioning from 1-bit mode to 4-bit reads has been fixed.
    This was causing the high speed write bug mentioned above.

    Read ID was stalling the bus. This was traced to a sign error while
    referencing the chip select line, and has been fixed.

    The lowerlevel QSPI project was modified to add a holding state. We were
    struggling with a bug whereby a late read would hang the device. The upper
    level driver would issue it when the lower level driver was busy, and yet
    think that it was accomplished. The lower level driver was moving from ready
    to idle, so it never saw the read. Now, hold keeps the lower level driver
    in the ready state at the end of a read until the bus transaction is complete,
    or until it goes on to some other transaction other than reading data.
    (This was a big change.)

    Finally, unnecessary debugging lines were disabled in the simulator.

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