URL https://opencores.org/ocsvn/sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk

Last modification

• Rev 136, 2010-10-15 13:28:18 GMT
• Author: tac2

• Log message:

  Updated.
  1. SD-model uppdated.
  2. Data transaction completion only when BD que is empty
  3. Card detect with debounce added to Normal_isr register bit, [1][2]
  4. Reset logic change, should be synthesizable in altera and xilinx devices, without need of modifications

Path
/sdcard_mass_storage_controller/trunk/bench/sdc_dma/verilog/sdModel.v
/sdcard_mass_storage_controller/trunk/bench/sdc_dma/verilog/sd_controller_top_tb.v
/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/verilog/sd_cmd_master.v
/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/verilog/sd_defines.v
/sdcard_mass_storage_controller/trunk/sim/rtl_sim/log/eth_tb_host.log
/sdcard_mass_storage_controller/trunk/sim/rtl_sim/log/eth_tb_phy.log
/sdcard_mass_storage_controller/trunk/sim/rtl_sim/log/eth_tb_wb_m_mon.log
/sdcard_mass_storage_controller/trunk/sim/rtl_sim/log/eth_tb_wb_s_mon.log
/sdcard_mass_storage_controller/trunk/sim/rtl_sim/log/sdc_tb.log
/sdcard_mass_storage_controller/trunk/sim/rtl_sim/log/sd_model.log
/sdcard_mass_storage_controller/trunk/sim/rtl_sim/log/sd_tb_memory.log
/sdcard_mass_storage_controller/trunk/sim/rtl_sim/run/comp.do