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Last modification

  • Rev 119, 2012-09-18 02:16:54 GMT
  • Author: jt_eaton
  • Log message:
    moved copyright files into /verilog
    changed cde copyright to apache from gplv3
    split out tools into separate subdirectories
    changed design.xml files to socgen: namespace
Path
/socgen/trunk/doc/src/guides/reset_sys_design.html
/socgen/trunk/Makefile
/socgen/trunk/projects/accellera
/socgen/trunk/projects/opencores.org/Basys/doc
/socgen/trunk/projects/opencores.org/Basys/ip/cde_clock/bin/Makefile
/socgen/trunk/projects/opencores.org/Basys/ip/cde_clock/rtl/verilog/syn/cde_clock_sys.v
/socgen/trunk/projects/opencores.org/Basys/ip/cde_clock/rtl/xml/cde_clock_sys.xml
/socgen/trunk/projects/opencores.org/Basys/ip/cde_jtag/doc/copyright.v
/socgen/trunk/projects/opencores.org/Basys/ip/cde_jtag/rtl/xml/cde_jtag_def.xml
/socgen/trunk/projects/opencores.org/Basys/ip/fpga/doc
/socgen/trunk/projects/opencores.org/Basys/ip/fpga/ip-xact/Basys_fpga_jtag_designCfg.xml
/socgen/trunk/projects/opencores.org/Basys/ip/fpga/rtl/xml/Basys_fpga_jtag_design.xml
/socgen/trunk/projects/opencores.org/Basys/ip/fpga/rtl/xml/Basys_fpga_jtag_padring.xml
/socgen/trunk/projects/opencores.org/Basys/ip/fpga/rtl/xml/Basys_fpga_padring.xml
/socgen/trunk/projects/opencores.org/Basys/ip/fpga/target
/socgen/trunk/projects/opencores.org/Busdefs/ip/clock/doc/copyright.v
/socgen/trunk/projects/opencores.org/Busdefs/ip/enable/doc/copyright.v
/socgen/trunk/projects/opencores.org/Busdefs/ip/ext_bus/doc/copyright.v
/socgen/trunk/projects/opencores.org/Busdefs/ip/jtag/doc/copyright.v
/socgen/trunk/projects/opencores.org/Busdefs/ip/micro_bus/doc/copyright.v
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/doc/copyright.v
/socgen/trunk/projects/opencores.org/Busdefs/ip/pad/doc/copyright.v
/socgen/trunk/projects/opencores.org/Busdefs/ip/ps2/doc/copyright.v
/socgen/trunk/projects/opencores.org/Busdefs/ip/reset/doc/copyright.v
/socgen/trunk/projects/opencores.org/Busdefs/ip/uart/doc/copyright.v
/socgen/trunk/projects/opencores.org/Busdefs/ip/vga/doc/copyright.v
/socgen/trunk/projects/opencores.org/Busdefs/ip/wishbone/doc/copyright.v
/socgen/trunk/projects/opencores.org/cde/bin/repeater
/socgen/trunk/projects/opencores.org/cde/doc/drawing/sym/cde_clock_sys.sym
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/ip-xact/cde_clock_gater.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/ip-xact/cde_clock_multiplier.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/ip-xact/cde_clock_sys.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/verilog/copyright.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/verilog/sim/cde_clock_diff_testmux.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/verilog/sim/cde_clock_dll.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/verilog/sim/cde_clock_gater.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/verilog/sim/cde_clock_multiplier.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/verilog/sim/cde_clock_sys.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/verilog/sim/cde_clock_testmux.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/verilog/syn/cde_clock_diff_testmux.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/verilog/syn/cde_clock_dll.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/verilog/syn/cde_clock_gater.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/verilog/syn/cde_clock_multiplier.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/verilog/syn/cde_clock_sys.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/verilog/syn/cde_clock_testmux.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_diff_testmux.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_diff_testmux.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_dll.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_gater.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_gater.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_multiplier.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_multiplier.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_sys.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_sys.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_testmux.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_testmux.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/soc
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/rtl/verilog/copyright.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/rtl/verilog/sim/cde_divider_def.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/rtl/verilog/syn/cde_divider_def.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/rtl/xml/cde_divider_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/soc
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/rtl/verilog/cde_fifo_def.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/rtl/verilog/copyright.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/rtl/xml/cde_fifo_def.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/rtl/xml/cde_fifo_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/soc
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/doc/copyright.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/ip-xact/cde_jtag_classic_rpc_in_reg.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/ip-xact/cde_jtag_classic_rpc_reg.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/ip-xact/cde_jtag_def.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/ip-xact/cde_jtag_rpc_in_reg.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/ip-xact/cde_jtag_rpc_reg.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/ip-xact/cde_jtag_tb.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/verilog/copyright.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/views/sim/cde_jtag_classic_rpc_in_reg.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/views/sim/cde_jtag_classic_rpc_reg.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/views/sim/cde_jtag_rpc_in_reg.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/views/sim/cde_jtag_rpc_reg.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/views/syn/cde_jtag_classic_rpc_in_reg.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/views/syn/cde_jtag_classic_rpc_reg.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/views/syn/cde_jtag_rpc_in_reg.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/views/syn/cde_jtag_rpc_reg.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_classic_rpc_in_reg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_classic_rpc_in_reg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_classic_rpc_reg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_classic_rpc_reg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_def.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_rpc_in_reg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_rpc_in_reg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_rpc_reg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_rpc_reg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/xml/cde_jtag_tb.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/xml/cde_jtag_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/soc
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/rtl/verilog/copyright.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/rtl/verilog/sim/cde_lifo_def.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/rtl/verilog/syn/cde_lifo_def.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/rtl/xml/cde_lifo_def.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/rtl/xml/cde_lifo_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/soc
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/doc/copyright.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/verilog/copyright.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/verilog/or1200_amultp2_32x32.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/verilog/top.asic
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/xml/cde_mult_asic.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/xml/cde_mult_generic.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/xml/cde_mult_ord_r4.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/xml/cde_mult_serial.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/icarus/asic
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/icarus/generic_64
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_asic_tb.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_asic_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_generic_64_tb.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_generic_64_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_generic_tb.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_generic_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_ord_r4_tb.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_ord_r4_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_serial_tb.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_serial_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/verilog/copyright.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/verilog/sim/cde_pad_diff_dig.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/verilog/sim/cde_pad_in_dig.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/verilog/sim/cde_pad_od_dig.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/verilog/sim/cde_pad_out_dig.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/verilog/sim/cde_pad_se_dig.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/verilog/syn/cde_pad_diff_dig.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/verilog/syn/cde_pad_in_dig.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/verilog/syn/cde_pad_od_dig.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/verilog/syn/cde_pad_out_dig.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/verilog/syn/cde_pad_se_dig.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_diff_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_in_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_od_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_out_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_se_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/soc
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/rtl/verilog/copyright.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/rtl/verilog/sim/cde_prescale.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/rtl/verilog/syn/cde_prescale.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/rtl/xml/cde_prescale_def.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/rtl/xml/cde_prescale_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/soc
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/ip-xact/cde_reset_def.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/verilog/copyright.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/verilog/sim/cde_reset.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/verilog/sim/cde_reset_asyncdisable.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/verilog/syn/cde_reset.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/verilog/syn/cde_reset_asyncdisable.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/xml/cde_reset_asyncdisable.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/xml/cde_reset_asyncdisable.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/xml/cde_reset_def.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/xml/cde_reset_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/soc
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/ip-xact/cde_serial_rcvr.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/ip-xact/cde_serial_xmit.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/rtl/verilog/copyright.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/rtl/verilog/sim/cde_serial_rcvr.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/rtl/verilog/sim/cde_serial_xmit.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/rtl/verilog/syn/cde_serial_rcvr.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/rtl/verilog/syn/cde_serial_xmit.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/rtl/xml/cde_serial_rcvr.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/rtl/xml/cde_serial_xmit.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/soc
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/cde_sram_be
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/cde_sram_def
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/cde_sram_dp
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/copyright.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/sim
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/syn
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/xml/cde_sram_be.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/xml/cde_sram_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/xml/cde_sram_dp.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/soc
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/ip-xact/cde_sync_def.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/ip-xact/cde_sync_with_hysteresis.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/verilog/copyright.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/verilog/sim/cde_sync.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/verilog/sim/cde_sync_with_hysteresis.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/verilog/sim/cde_sync_with_reset.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/verilog/syn/cde_sync.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/verilog/syn/cde_sync_with_hysteresis.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/verilog/syn/cde_sync_with_reset.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/xml/cde_sync_def.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/xml/cde_sync_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/xml/cde_sync_with_hysteresis.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/xml/cde_sync_with_hysteresis.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/xml/cde_sync_with_reset.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/xml/cde_sync_with_reset.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/soc
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/doc/copyright.v
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/socgen/trunk/tools/verilog/gen_verilogLib
/socgen/trunk/tools/yp/hier_index.xml
/socgen/trunk/tools/yp/index.xml

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