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Last modification

  • Rev 104, 2012-03-04 01:07:44 GMT
  • Author: jt_eaton
  • Log message:
    fixed search in preprocessor script
    added initial orp_soc project
Path
/socgen/trunk/projects/opencores.org/orp_soc
/socgen/trunk/projects/opencores.org/orp_soc/bin
/socgen/trunk/projects/opencores.org/orp_soc/bin/Makefile.or32
/socgen/trunk/projects/opencores.org/orp_soc/bin/repeater
/socgen/trunk/projects/opencores.org/orp_soc/doc
/socgen/trunk/projects/opencores.org/orp_soc/doc/pdf
/socgen/trunk/projects/opencores.org/orp_soc/doc/src
/socgen/trunk/projects/opencores.org/orp_soc/doc/src/case_or1k.html
/socgen/trunk/projects/opencores.org/orp_soc/doc/src/drawing
/socgen/trunk/projects/opencores.org/orp_soc/doc/src/drawing/sch
/socgen/trunk/projects/opencores.org/orp_soc/doc/src/drawing/sym
/socgen/trunk/projects/opencores.org/orp_soc/doc/src/journal.html
/socgen/trunk/projects/opencores.org/orp_soc/doc/src/png
/socgen/trunk/projects/opencores.org/orp_soc/doc/src/slides
/socgen/trunk/projects/opencores.org/orp_soc/ip
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/doc
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/doc/copyright.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/ip-xact
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/ip-xact/generic_orpsocv2_ra_ti_ua.designCfg.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/arbiter
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/arbiter/arbiter_bytebus.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/arbiter/arbiter_dbus.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/arbiter/arbiter_ibus.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/arbiter/README
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/clkgen
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/clkgen/clkgen.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/clkgen/README
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/dbg_cpu_defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/dbg_defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/dbg_if
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/dbg_if/dbg_cpu.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/dbg_if/dbg_cpu_registers.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/dbg_if/dbg_crc32_d1.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/dbg_if/dbg_if.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/dbg_if/dbg_register.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/dbg_if/dbg_wb.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/dbg_wb_defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/intgen
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/intgen/intgen.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/jtag_tap
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/jtag_tap/jtag_tap.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/jtag_tap/README
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_alu.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_amultp2_32x32.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_cfgr.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_cpu.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_ctrl.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_dc_fsm.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_dc_ram.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_dc_tag.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_dc_top.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_dmmu_tlb.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_dmmu_top.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_dpram.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_dpram_32x32.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_dpram_256x32.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_du.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_except.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_fpu.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_fpu_addsub.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_fpu_arith.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_fpu_div.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_fpu_fcmp.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_fpu_intfloat_conv.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_fpu_mul.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_fpu_post_norm_addsub.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_fpu_post_norm_div.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_fpu_post_norm_intfloat_conv.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_fpu_post_norm_mul.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_fpu_pre_norm_addsub.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_fpu_pre_norm_div.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_fpu_pre_norm_mul.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_freeze.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_genpc.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_gmultp2_32x32.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_ic_fsm.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_ic_ram.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_ic_tag.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_ic_top.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_if.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_immu_tlb.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_immu_top.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_iwb_biu.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_lsu.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_mem2reg.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_operandmuxes.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_pic.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_pm.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_qmem_top.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_reg2mem.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_rf.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_rfram_generic.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_sb.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_sb_fifo.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_spram.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_spram_32x24.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_spram_32_bw.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_spram_64x14.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_spram_64x22.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_spram_64x24.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_spram_128x32.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_spram_256x21.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_spram_512x20.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_spram_1024x8.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_spram_1024x32.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_spram_1024x32_bw.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_spram_2048x8.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_spram_2048x32.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_spram_2048x32_bw.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_sprs.v
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/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_tpram_32x32.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_tt.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_wbmux.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_wb_biu.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_xcv_ram32x8d.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200_defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/orpsoc-defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/orpsoc-params.v
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/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/ram_wb/ram_wb.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/tap_defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/timescale.v
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/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/uart16550
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/uart16550/raminfr.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/uart16550/README
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/uart16550/uart16550.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/uart16550/uart_debug_if.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/uart16550/uart_receiver.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/uart16550/uart_regs.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/uart16550/uart_rfifo.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/uart16550/uart_sync_flops.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/uart16550/uart_tfifo.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/uart16550/uart_transmitter.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/uart16550/uart_wb.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/uart_defines.v
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/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/xml/generic_orpsocv2_ra_ti_ua.design.xml
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/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-dctest/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-dctest/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-div
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-div/dmp_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-div/sram.vmem
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-div/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-div/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-except
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-except/dmp_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-except/sram.vmem
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-except/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-except/wave.sav
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