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Last modification

  • Rev 111, 2012-03-30 21:29:07 GMT
  • Author: jt_eaton
  • Log message:
    split or1200 out into seperate test suite
Path
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/sim/cde_sram_def.v
/socgen/trunk/projects/opencores.org/orp_soc/bin/Makefile.or32
/socgen/trunk/projects/opencores.org/orp_soc/doc/pdf/journal.pdf
/socgen/trunk/projects/opencores.org/orp_soc/doc/src/journal.html
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/jtag_cpu-basic
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/jtag_cpu-basic/dmp_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/jtag_cpu-basic/sram.vmem
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/jtag_cpu-basic/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/jtag_cpu-basic/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/jtag_wb-basic
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/jtag_wb-basic/dmp_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/jtag_wb-basic/sram.vmem
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/jtag_wb-basic/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/jtag_wb-basic/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/ip-xact/or1200_dbg_tb.designCfg.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/bin/Makefile
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-basic
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-basic/dmp_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-basic/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-basic/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-basic_sprs_tt
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-basic_sprs_tt/dmp_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-basic_sprs_tt/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-basic_sprs_tt/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-cy
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-cy/dmp_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-cy/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-cy/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-div
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-div/dmp_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-div/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-div/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-ext
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-ext/dmp_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-ext/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-ext/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-ffl1
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-ffl1/dmp_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-ffl1/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-ffl1/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-mac
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-mac/dmp_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-mac/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-mac/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-maci
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-maci/dmp_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-maci/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-maci/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-mul
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-mul/dmp_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-mul/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-mul/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-no_code_sprs_du
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-no_code_sprs_du/dmp_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-no_code_sprs_du/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-no_code_sprs_du/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-no_code_sprs_sys
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-no_code_sprs_sys/dmp_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-no_code_sprs_sys/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-no_code_sprs_sys/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-ov
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-ov/dmp_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-ov/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-ov/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-pm
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-pm/dmp_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-pm/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-pm/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-rfe
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-rfe/dmp_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-rfe/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-rfe/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-sf
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-sf/dmp_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-sf/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-sf/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-simple
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-simple/dmp_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-simple/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/icarus/or1200-simple/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/verilog
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/verilog/top.rtl
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/xml/or1200_dbg_tb.design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/xml/or1200_dbg_tb.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/top.rtl
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/sim/icarus/or1200-dctest/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/sim/icarus/or1200-tick/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/sim/verilog/top.rtl
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/sim/xml/orpsocv2_ra_ti_ua_tb.design.xml
/socgen/trunk/projects/opencores.org/orp_soc/sw/or1200-div/Makefile
/socgen/trunk/projects/opencores.org/orp_soc/sw/or1200-mul/Makefile
/socgen/trunk/projects/opencores.org/orp_soc/sw/or1200-simple/Makefile
/socgen/trunk/projects/opencores.org/Testbench/ip/or1200_dbg_model
/socgen/trunk/projects/opencores.org/Testbench/ip/or1200_dbg_model/bin
/socgen/trunk/projects/opencores.org/Testbench/ip/or1200_dbg_model/bin/Makefile
/socgen/trunk/projects/opencores.org/Testbench/ip/or1200_dbg_model/doc
/socgen/trunk/projects/opencores.org/Testbench/ip/or1200_dbg_model/doc/copyright.v
/socgen/trunk/projects/opencores.org/Testbench/ip/or1200_dbg_model/doc/html
/socgen/trunk/projects/opencores.org/Testbench/ip/or1200_dbg_model/doc/png
/socgen/trunk/projects/opencores.org/Testbench/ip/or1200_dbg_model/doc/timing
/socgen/trunk/projects/opencores.org/Testbench/ip/or1200_dbg_model/ip-xact
/socgen/trunk/projects/opencores.org/Testbench/ip/or1200_dbg_model/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/or1200_dbg_model/ip-xact/micro_bus_model_def.designCfg.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/or1200_dbg_model/rtl
/socgen/trunk/projects/opencores.org/Testbench/ip/or1200_dbg_model/rtl/verilog
/socgen/trunk/projects/opencores.org/Testbench/ip/or1200_dbg_model/rtl/verilog/top.task
/socgen/trunk/projects/opencores.org/Testbench/ip/or1200_dbg_model/rtl/xml
/socgen/trunk/projects/opencores.org/Testbench/ip/or1200_dbg_model/rtl/xml/or1200_dbg_model_def.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/or1200_dbg_model/sim
/socgen/trunk/projects/opencores.org/Testbench/ip/or1200_dbg_model/sim/xml
/socgen/trunk/projects/opencores.org/Testbench/ip/or1200_dbg_model/soc

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