OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] - Rev 83

Rev

Directory listing | View Log | Compare with Previous | RSS feed

Last modification

  • Rev 83, 2011-01-21 20:11:28 GMT
  • Author: jt_eaton
  • Log message:
    added design.soc files
    xml files now 99% 1685 complient
Path
/socgen/trunk/Makefile
/socgen/trunk/projects/io/ip/io_ext_mem_interface/rtl/verilog/top
/socgen/trunk/projects/io/ip/io_ext_mem_interface/rtl/xml/io_ext_mem_interface.xml
/socgen/trunk/projects/io/ip/io_ext_mem_interface/soc
/socgen/trunk/projects/io/ip/io_ext_mem_interface/soc/design.soc
/socgen/trunk/projects/io/ip/io_gpio/rtl/verilog/top
/socgen/trunk/projects/io/ip/io_gpio/rtl/xml/io_gpio.xml
/socgen/trunk/projects/io/ip/io_gpio/soc
/socgen/trunk/projects/io/ip/io_gpio/soc/design.soc
/socgen/trunk/projects/io/ip/io_module/rtl/verilog
/socgen/trunk/projects/io/ip/io_module/rtl/verilog/top.mouse.rtl
/socgen/trunk/projects/io/ip/io_module/rtl/verilog/top.rtl
/socgen/trunk/projects/io/ip/io_module/rtl/xml/io_module.xml
/socgen/trunk/projects/io/ip/io_module/rtl/xml/io_module_mouse.xml
/socgen/trunk/projects/io/ip/io_module/soc
/socgen/trunk/projects/io/ip/io_module/soc/design.soc
/socgen/trunk/projects/io/ip/io_pic/rtl/verilog/micro_reg
/socgen/trunk/projects/io/ip/io_pic/rtl/verilog/top
/socgen/trunk/projects/io/ip/io_pic/rtl/xml/io_pic.xml
/socgen/trunk/projects/io/ip/io_pic/soc
/socgen/trunk/projects/io/ip/io_pic/soc/design.soc
/socgen/trunk/projects/io/ip/io_ps2/rtl/verilog/micro_reg
/socgen/trunk/projects/io/ip/io_ps2/rtl/verilog/top
/socgen/trunk/projects/io/ip/io_ps2/rtl/xml/io_ps2.xml
/socgen/trunk/projects/io/ip/io_ps2/soc
/socgen/trunk/projects/io/ip/io_ps2/soc/design.soc
/socgen/trunk/projects/io/ip/io_timer/rtl/verilog/micro_reg
/socgen/trunk/projects/io/ip/io_timer/rtl/verilog/top
/socgen/trunk/projects/io/ip/io_timer/rtl/xml/io_timer.xml
/socgen/trunk/projects/io/ip/io_timer/soc
/socgen/trunk/projects/io/ip/io_timer/soc/design.soc
/socgen/trunk/projects/io/ip/io_uart/rtl/verilog/micro_reg
/socgen/trunk/projects/io/ip/io_uart/rtl/verilog/top
/socgen/trunk/projects/io/ip/io_uart/rtl/xml/io_uart.xml
/socgen/trunk/projects/io/ip/io_uart/soc
/socgen/trunk/projects/io/ip/io_uart/soc/design.soc
/socgen/trunk/projects/io/ip/io_utimer/rtl/verilog/micro_reg
/socgen/trunk/projects/io/ip/io_utimer/rtl/verilog/top
/socgen/trunk/projects/io/ip/io_utimer/rtl/xml/io_utimer.xml
/socgen/trunk/projects/io/ip/io_utimer/soc
/socgen/trunk/projects/io/ip/io_utimer/soc/design.soc
/socgen/trunk/projects/io/ip/io_vga/rtl/verilog/micro_reg
/socgen/trunk/projects/io/ip/io_vga/rtl/verilog/top
/socgen/trunk/projects/io/ip/io_vga/rtl/xml/io_vga.xml
/socgen/trunk/projects/io/ip/io_vga/soc
/socgen/trunk/projects/io/ip/io_vga/soc/design.soc
/socgen/trunk/projects/io/ip/io_vic/rtl/verilog/top
/socgen/trunk/projects/io/ip/io_vic/rtl/xml/io_vic.xml
/socgen/trunk/projects/io/ip/io_vic/soc
/socgen/trunk/projects/io/ip/io_vic/soc/design.soc
/socgen/trunk/projects/logic/ip/disp_io/rtl/verilog/top
/socgen/trunk/projects/logic/ip/disp_io/rtl/xml/disp_io.xml
/socgen/trunk/projects/logic/ip/disp_io/soc
/socgen/trunk/projects/logic/ip/disp_io/soc/design.soc
/socgen/trunk/projects/logic/ip/flash_memcontrl/rtl/verilog/top
/socgen/trunk/projects/logic/ip/flash_memcontrl/rtl/xml/flash_memcontrl.xml
/socgen/trunk/projects/logic/ip/flash_memcontrl/soc
/socgen/trunk/projects/logic/ip/flash_memcontrl/soc/design.soc
/socgen/trunk/projects/logic/ip/micro_bus/rtl/verilog/top
/socgen/trunk/projects/logic/ip/micro_bus/rtl/xml/micro_bus.xml
/socgen/trunk/projects/logic/ip/micro_bus/soc
/socgen/trunk/projects/logic/ip/micro_bus/soc/design.soc
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/verilog/fsm
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/verilog/top
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/xml/ps2_interface.xml
/socgen/trunk/projects/logic/ip/ps2_interface/soc
/socgen/trunk/projects/logic/ip/ps2_interface/soc/design.soc
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/verilog/top
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/xml/serial_rcvr.xml
/socgen/trunk/projects/logic/ip/serial_rcvr/soc
/socgen/trunk/projects/logic/ip/serial_rcvr/soc/design.soc
/socgen/trunk/projects/logic/ip/uart/rtl/verilog/top
/socgen/trunk/projects/logic/ip/uart/rtl/xml/uart.xml
/socgen/trunk/projects/logic/ip/uart/soc
/socgen/trunk/projects/logic/ip/uart/soc/design.soc
/socgen/trunk/projects/logic/ip/usb_epp/rtl/verilog/top
/socgen/trunk/projects/logic/ip/usb_epp/rtl/xml/usb_epp.xml
/socgen/trunk/projects/logic/ip/usb_epp/soc
/socgen/trunk/projects/logic/ip/usb_epp/soc/design.soc
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/char_display
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/char_gen
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/svga_timing_generation
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/top
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/video_out
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl.xml
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl_600x432.xml
/socgen/trunk/projects/logic/ip/vga_char_ctrl/soc
/socgen/trunk/projects/logic/ip/vga_char_ctrl/soc/design.soc
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/top.rtl
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502.xml
/socgen/trunk/projects/Mos6502/ip/T6502/soc
/socgen/trunk/projects/Mos6502/ip/T6502/soc/design.soc
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/xml/T6502_cpu.xml
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/soc
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/soc/design.soc
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/rtl/verilog/top
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/rtl/xml/T6502_cpu_alu_logic.xml
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/soc
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/soc/design.soc
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/soc
/socgen/trunk/projects/pic_micro/ip/mrisc/soc/design.soc
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/alu
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/fifo
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/presclr_wdt
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/register_file
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/top
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/soc
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/soc/design.soc
/socgen/trunk/projects/pic_micro/ip/soc/rtl/verilog
/socgen/trunk/projects/pic_micro/ip/soc/rtl/verilog/top.rtl
/socgen/trunk/projects/pic_micro/ip/soc/rtl/xml/soc_mrisc_io.xml
/socgen/trunk/projects/pic_micro/ip/soc/soc
/socgen/trunk/projects/pic_micro/ip/soc/soc/design.soc
/socgen/trunk/tools/bin/build_filelists
/socgen/trunk/tools/bin/build_leaf
/socgen/trunk/tools/bin/build_verilog
/socgen/trunk/tools/bin/Makefile.root
/socgen/trunk/tools/bin/setup_cov
/socgen/trunk/tools/bin/soc_builder
/socgen/trunk/tools/bin/soc_link

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.