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[/] [spi_master_slave/] - Rev 12


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Last modification

  • Rev 12, 2011-07-29 05:27:38 GMT
  • Author: jdoin
  • Log message:
    SPI_SLAVE: v2.00.0110 [JD] FIX: CPHA bugs:
    -- - redesigned core clocking to address all CPOL and CPHA configurations.
    -- - added CHANGE_EDGE to the FSM register transfer logic, to have MISO change at opposite
    -- clock phases from SHIFT_EDGE.
    -- Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
    -- for each state, to avoid reported inference problems in some synthesis engines.
    -- Streamlined port names and indentation blocks.

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