URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

[/] - Rev 14

Rev 14, 2010-01-18 07:28:13 GMT
Author: ghutchis
Log message:
- Modified large FIFO to remove "full" signal and store only N-1 words
- changed small FIFO to use memory instance instead of registers
- changed sequence generator to enable more complex tests
- changed sd_mirror to use combinatorial assign output

Path
/srdydrdy_lib/trunk/env/verilog/bench_fifo_b.v
/srdydrdy_lib/trunk/env/verilog/bench_fifo_s.v
/srdydrdy_lib/trunk/env/verilog/bench_fifo_s.vf
/srdydrdy_lib/trunk/env/verilog/sd_seq_gen.v
/srdydrdy_lib/trunk/examples/bridge/env/run
/srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_head_b.v
/srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_s.v
/srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_tail_b.v
/srdydrdy_lib/trunk/rtl/verilog/forks/sd_mirror.v