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URL https://opencores.org/ocsvn/storm_soc/storm_soc/trunk

Subversion Repositories storm_soc

[/] - Rev 2

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Last modification

  • Rev 2, 2012-03-20 23:26:10 GMT
  • Author: zero_gravity
  • Log message:
    - initial repository setup
    - MAIN TOP ENTITY STILL MISSING!
    - SYN STILL MISSING!
Path
/storm_soc/trunk/components
/storm_soc/trunk/components/boot rom
/storm_soc/trunk/components/boot rom/rtl
/storm_soc/trunk/components/boot rom/rtl/BOOT_ROM_FILE.vhd
/storm_soc/trunk/components/i2c controller
/storm_soc/trunk/components/i2c controller/doc
/storm_soc/trunk/components/i2c controller/doc/i2c_specs.pdf
/storm_soc/trunk/components/i2c controller/rtl
/storm_soc/trunk/components/i2c controller/rtl/vhdl
/storm_soc/trunk/components/i2c controller/rtl/vhdl/i2c_master_bit_ctrl.vhd
/storm_soc/trunk/components/i2c controller/rtl/vhdl/i2c_master_byte_ctrl.vhd
/storm_soc/trunk/components/i2c controller/rtl/vhdl/i2c_master_top.vhd
/storm_soc/trunk/components/i2c controller/rtl/vhdl/readme
/storm_soc/trunk/components/i2c controller/software
/storm_soc/trunk/components/i2c controller/software/include
/storm_soc/trunk/components/i2c controller/software/include/oc_i2c_master.h
/storm_soc/trunk/components/io controller
/storm_soc/trunk/components/io controller/rtl
/storm_soc/trunk/components/io controller/rtl/GP_IO_CTRL.vhd
/storm_soc/trunk/components/mem_ctrl
/storm_soc/trunk/components/mem_ctrl/bench
/storm_soc/trunk/components/mem_ctrl/bench/richard
/storm_soc/trunk/components/mem_ctrl/bench/richard/verilog
/storm_soc/trunk/components/mem_ctrl/bench/richard/verilog/bench.v
/storm_soc/trunk/components/mem_ctrl/bench/richard/verilog/checkers.v
/storm_soc/trunk/components/mem_ctrl/bench/richard/verilog/mc_defines.v
/storm_soc/trunk/components/mem_ctrl/bench/richard/verilog/models
/storm_soc/trunk/components/mem_ctrl/bench/richard/verilog/models/m8kx8.v
/storm_soc/trunk/components/mem_ctrl/bench/richard/verilog/models/mt48lc16m16a2.v
/storm_soc/trunk/components/mem_ctrl/bench/richard/verilog/models/mt58l1my18d.v
/storm_soc/trunk/components/mem_ctrl/bench/richard/verilog/timescale.v
/storm_soc/trunk/components/mem_ctrl/bench/richard/verilog/tst_asram.v
/storm_soc/trunk/components/mem_ctrl/bench/richard/verilog/tst_multi_mem.v
/storm_soc/trunk/components/mem_ctrl/bench/richard/verilog/tst_sdram.v
/storm_soc/trunk/components/mem_ctrl/bench/richard/verilog/tst_ssram.v
/storm_soc/trunk/components/mem_ctrl/bench/richard/verilog/wb_master_model.v
/storm_soc/trunk/components/mem_ctrl/bench/verilog
/storm_soc/trunk/components/mem_ctrl/bench/verilog/160b3ver
/storm_soc/trunk/components/mem_ctrl/bench/verilog/160b3ver/adv_bb.v
/storm_soc/trunk/components/mem_ctrl/bench/verilog/160b3ver/dp160b3b.v
/storm_soc/trunk/components/mem_ctrl/bench/verilog/160b3ver/DP160B3B_RU.V
/storm_soc/trunk/components/mem_ctrl/bench/verilog/160b3ver/dp160b3t.v
/storm_soc/trunk/components/mem_ctrl/bench/verilog/160b3ver/f160b3b.bkb
/storm_soc/trunk/components/mem_ctrl/bench/verilog/160b3ver/f160b3b.bke
/storm_soc/trunk/components/mem_ctrl/bench/verilog/160b3ver/f160b3b.bkt
/storm_soc/trunk/components/mem_ctrl/bench/verilog/160b3ver/f160b3t.bkb
/storm_soc/trunk/components/mem_ctrl/bench/verilog/160b3ver/f160b3t.bke
/storm_soc/trunk/components/mem_ctrl/bench/verilog/160b3ver/f160b3t.bkt
/storm_soc/trunk/components/mem_ctrl/bench/verilog/160b3ver/read.me
/storm_soc/trunk/components/mem_ctrl/bench/verilog/160b3ver/t160b3b.v
/storm_soc/trunk/components/mem_ctrl/bench/verilog/160b3ver/t160b3t.v
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/2Mx32
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/2Mx32/bank0.txt
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/2Mx32/bank1.txt
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/2Mx32/bank2.txt
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/2Mx32/bank3.txt
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/2Mx32/mt48lc2m32b2.v
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/4Mx16
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/4Mx16/bank0.txt
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/4Mx16/bank1.txt
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/4Mx16/bank2.txt
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/4Mx16/bank3.txt
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/4Mx16/mt48lc4m16a2.v
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/4Mx32
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/4Mx32/mt48lc4m32b2.v
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/8Mx8
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/8Mx8/bank0.txt
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/8Mx8/bank1.txt
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/8Mx8/bank2.txt
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/8Mx8/bank3.txt
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/8Mx8/mt48lc8m8a2.v
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/8Mx16
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/8Mx16/mt48lc8m16a2.v
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/16Mx8
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/16Mx8/mt48lc16m8a2.v
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/16Mx16
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/16Mx16/mt48lc16m16a2.v
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/32Mx8
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sdram_models/32Mx8/mt48lc32m8a2.v
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sram_models
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sram_models/IDT71T67802
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sram_models/IDT71T67802/idt71t67802s133.v
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sram_models/IDT71T67802/idt71t67802s150.v
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sram_models/IDT71T67802/idt71t67802s166.v
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sram_models/IDT71T67802/idt_512Kx18_PBSRAM_test.v
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sram_models/IDT71T67802/readme_71T67802
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sram_models/MicronSRAM
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sram_models/MicronSRAM/mt58l1my18d.v
/storm_soc/trunk/components/mem_ctrl/bench/verilog/sync_cs_dev.v
/storm_soc/trunk/components/mem_ctrl/bench/verilog/tests.v
/storm_soc/trunk/components/mem_ctrl/bench/verilog/test_bench_top.v
/storm_soc/trunk/components/mem_ctrl/bench/verilog/test_lib.v
/storm_soc/trunk/components/mem_ctrl/bench/verilog/wb_mast_model.v
/storm_soc/trunk/components/mem_ctrl/bench/verilog/wb_model_defines.v
/storm_soc/trunk/components/mem_ctrl/bench/vhdl
/storm_soc/trunk/components/mem_ctrl/bench/vhdl/8Kx8_vhdl.vhd
/storm_soc/trunk/components/mem_ctrl/bench/vhdl/mt48lc2m32b2.v
/storm_soc/trunk/components/mem_ctrl/bench/vhdl/mt58l64l32p.v
/storm_soc/trunk/components/mem_ctrl/bench/vhdl/tst_bench.vhd
/storm_soc/trunk/components/mem_ctrl/doc
/storm_soc/trunk/components/mem_ctrl/doc/mc_doc.pdf
/storm_soc/trunk/components/mem_ctrl/doc/README.txt
/storm_soc/trunk/components/mem_ctrl/doc/STATUS.txt
/storm_soc/trunk/components/mem_ctrl/rtl
/storm_soc/trunk/components/mem_ctrl/rtl/verilog
/storm_soc/trunk/components/mem_ctrl/rtl/verilog/mc_adr_sel.v
/storm_soc/trunk/components/mem_ctrl/rtl/verilog/mc_cs_rf.v
/storm_soc/trunk/components/mem_ctrl/rtl/verilog/mc_defines.v
/storm_soc/trunk/components/mem_ctrl/rtl/verilog/mc_dp.v
/storm_soc/trunk/components/mem_ctrl/rtl/verilog/mc_incn_r.v
/storm_soc/trunk/components/mem_ctrl/rtl/verilog/mc_mem_if.v
/storm_soc/trunk/components/mem_ctrl/rtl/verilog/mc_obct.v
/storm_soc/trunk/components/mem_ctrl/rtl/verilog/mc_obct_top.v
/storm_soc/trunk/components/mem_ctrl/rtl/verilog/mc_rd_fifo.v
/storm_soc/trunk/components/mem_ctrl/rtl/verilog/mc_refresh.v
/storm_soc/trunk/components/mem_ctrl/rtl/verilog/mc_rf.v
/storm_soc/trunk/components/mem_ctrl/rtl/verilog/mc_timing.v
/storm_soc/trunk/components/mem_ctrl/rtl/verilog/mc_top.v
/storm_soc/trunk/components/mem_ctrl/rtl/verilog/mc_wb_if.v
/storm_soc/trunk/components/mem_ctrl/sim
/storm_soc/trunk/components/mem_ctrl/sim/rtl_sim
/storm_soc/trunk/components/mem_ctrl/sim/rtl_sim/bin
/storm_soc/trunk/components/mem_ctrl/sim/rtl_sim/bin/Makefile
/storm_soc/trunk/components/mem_ctrl/sim/rtl_sim/richard
/storm_soc/trunk/components/mem_ctrl/sim/rtl_sim/richard/run
/storm_soc/trunk/components/mem_ctrl/sim/rtl_sim/richard/run/run
/storm_soc/trunk/components/mem_ctrl/sim/vhdl_rtl_sim
/storm_soc/trunk/components/mem_ctrl/sim/vhdl_rtl_sim/bin
/storm_soc/trunk/components/mem_ctrl/sim/vhdl_rtl_sim/bin/Makefile
/storm_soc/trunk/components/miniuart
/storm_soc/trunk/components/miniuart/doc
/storm_soc/trunk/components/miniuart/doc/MiniUart.pdf
/storm_soc/trunk/components/miniuart/rtl
/storm_soc/trunk/components/miniuart/rtl/vhdl
/storm_soc/trunk/components/miniuart/rtl/vhdl/MINI_UART.vhd
/storm_soc/trunk/components/miniuart/rtl/vhdl/Rxunit.vhd
/storm_soc/trunk/components/miniuart/rtl/vhdl/Txunit.vhd
/storm_soc/trunk/components/miniuart/rtl/vhdl/utils.vhd
/storm_soc/trunk/components/ps2core
/storm_soc/trunk/components/ps2core/rtl
/storm_soc/trunk/components/ps2core/rtl/vhdl
/storm_soc/trunk/components/ps2core/rtl/vhdl/ps2.vhd
/storm_soc/trunk/components/ps2core/rtl/vhdl/ps2_wb.vhd
/storm_soc/trunk/components/reset protector
/storm_soc/trunk/components/reset protector/rtl
/storm_soc/trunk/components/reset protector/rtl/RST_PROTECT.vhd
/storm_soc/trunk/components/seven segment controller
/storm_soc/trunk/components/seven segment controller/rtl
/storm_soc/trunk/components/seven segment controller/rtl/SEVEN_SEG_CTRL.vhd
/storm_soc/trunk/components/spi controller
/storm_soc/trunk/components/spi controller/doc
/storm_soc/trunk/components/spi controller/doc/spi.pdf
/storm_soc/trunk/components/spi controller/rtl
/storm_soc/trunk/components/spi controller/rtl/verilog
/storm_soc/trunk/components/spi controller/rtl/verilog/spi_clgen.v
/storm_soc/trunk/components/spi controller/rtl/verilog/spi_defines.v
/storm_soc/trunk/components/spi controller/rtl/verilog/spi_shift.v
/storm_soc/trunk/components/spi controller/rtl/verilog/spi_top.v
/storm_soc/trunk/components/spi controller/rtl/verilog/timescale.v
/storm_soc/trunk/components/sram memory
/storm_soc/trunk/components/sram memory/rtl
/storm_soc/trunk/components/sram memory/rtl/MEMORY.vhd
/storm_soc/trunk/components/timer
/storm_soc/trunk/components/timer/rtl
/storm_soc/trunk/components/timer/rtl/TIMER.vhd
/storm_soc/trunk/components/vector interrupt controller
/storm_soc/trunk/components/vector interrupt controller/rtl
/storm_soc/trunk/components/vector interrupt controller/rtl/VIC.vhd
/storm_soc/trunk/doc
/storm_soc/trunk/doc/STORM SoC - Altera DE2-Board Implementation.pdf
/storm_soc/trunk/doc/STORM SoC - System Components.pdf
/storm_soc/trunk/doc/wbspec_b4.pdf
/storm_soc/trunk/implementations
/storm_soc/trunk/tools
/storm_soc/trunk/tools/Terminal.exe

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