OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] - Rev 342

Rev

Directory listing | View Log | Compare with Previous | RSS feed

Last modification

  • Rev 342, 2023-01-27 17:47:04 GMT
  • Author: arniml
  • Log message:
    merge branch wip_t2x into trunk
Path
/t48/trunk
/t48/trunk/bench/vhdl/tb_t8021-c.vhd
/t48/trunk/bench/vhdl/tb_t8021.vhd
/t48/trunk/bench/vhdl/tb_t8022-c.vhd
/t48/trunk/bench/vhdl/tb_t8022.vhd
/t48/trunk/CHANGELOG
/t48/trunk/COMPILE_LIST
/t48/trunk/doc/src/T48 Integration Manual.odt
/t48/trunk/doc/T48 Integration Manual.pdf
/t48/trunk/README
/t48/trunk/rtl/vhdl/adc-c.vhd
/t48/trunk/rtl/vhdl/adc.vhd
/t48/trunk/rtl/vhdl/bus_mux.vhd
/t48/trunk/rtl/vhdl/decoder.vhd
/t48/trunk/rtl/vhdl/decoder_pack-p.vhd
/t48/trunk/rtl/vhdl/int.vhd
/t48/trunk/rtl/vhdl/system/t48_system_comp_pack-p.vhd
/t48/trunk/rtl/vhdl/system/t8021-c.vhd
/t48/trunk/rtl/vhdl/system/t8021.vhd
/t48/trunk/rtl/vhdl/system/t8021_notri-c.vhd
/t48/trunk/rtl/vhdl/system/t8021_notri.vhd
/t48/trunk/rtl/vhdl/system/t8022-c.vhd
/t48/trunk/rtl/vhdl/system/t8022.vhd
/t48/trunk/rtl/vhdl/system/t8022_notri-c.vhd
/t48/trunk/rtl/vhdl/system/t8022_notri.vhd
/t48/trunk/rtl/vhdl/t21_core-c.vhd
/t48/trunk/rtl/vhdl/t21_core.vhd
/t48/trunk/rtl/vhdl/t22_core-c.vhd
/t48/trunk/rtl/vhdl/t22_core.vhd
/t48/trunk/rtl/vhdl/t48_comp_pack-p.vhd
/t48/trunk/rtl/vhdl/t48_core_comp_pack-p.vhd
/t48/trunk/sim/rtl_sim/Makefile.ghdl
/t48/trunk/sim/rtl_sim/Makefile.hier
/t48/trunk/sw/run_regression.pl
/t48/trunk/sw/verif/black_box/add/a_data/no_t21
/t48/trunk/sw/verif/black_box/add/a_data/no_t22
/t48/trunk/sw/verif/black_box/add/rr/no_t21
/t48/trunk/sw/verif/black_box/add/rr/no_t22
/t48/trunk/sw/verif/black_box/addc/rr/no_t21
/t48/trunk/sw/verif/black_box/addc/rr/no_t22
/t48/trunk/sw/verif/black_box/anl/bus/no_t21
/t48/trunk/sw/verif/black_box/anl/bus/no_t22
/t48/trunk/sw/verif/black_box/anl/pp/no_t21
/t48/trunk/sw/verif/black_box/anl/pp/no_t22
/t48/trunk/sw/verif/black_box/anl/rr/no_t21
/t48/trunk/sw/verif/black_box/anl/rr/no_t22
/t48/trunk/sw/verif/black_box/call/call_ret/no_t21
/t48/trunk/sw/verif/black_box/call/call_ret/no_t22
/t48/trunk/sw/verif/black_box/call/simple/no_t21
/t48/trunk/sw/verif/black_box/call/simple/no_t22
/t48/trunk/sw/verif/black_box/clr/a/test.asm
/t48/trunk/sw/verif/black_box/clr/f0/no_t21
/t48/trunk/sw/verif/black_box/clr/f0/no_t22
/t48/trunk/sw/verif/black_box/clr/f1/no_t21
/t48/trunk/sw/verif/black_box/clr/f1/no_t22
/t48/trunk/sw/verif/black_box/cnt/cnt/test.asm
/t48/trunk/sw/verif/black_box/cnt/int/no_t21
/t48/trunk/sw/verif/black_box/cnt/int/no_t22
/t48/trunk/sw/verif/black_box/cpl/f0/no_t21
/t48/trunk/sw/verif/black_box/cpl/f0/no_t22
/t48/trunk/sw/verif/black_box/cpl/f1/no_t21
/t48/trunk/sw/verif/black_box/cpl/f1/no_t22
/t48/trunk/sw/verif/black_box/da/no_t21
/t48/trunk/sw/verif/black_box/da/no_t22
/t48/trunk/sw/verif/black_box/dec/a/test.asm
/t48/trunk/sw/verif/black_box/dec/rr/no_t21
/t48/trunk/sw/verif/black_box/dec/rr/no_t22
/t48/trunk/sw/verif/black_box/in/no_t21
/t48/trunk/sw/verif/black_box/in/no_t22
/t48/trunk/sw/verif/black_box/inc/a/test.asm
/t48/trunk/sw/verif/black_box/inc/rr/no_t21
/t48/trunk/sw/verif/black_box/inc/rr/no_t22
/t48/trunk/sw/verif/black_box/ins/no_t21
/t48/trunk/sw/verif/black_box/ins/no_t22
/t48/trunk/sw/verif/black_box/int/jni/no_t21
/t48/trunk/sw/verif/black_box/int/jni/no_t22
/t48/trunk/sw/verif/black_box/int/simple_int_retr/no_t21
/t48/trunk/sw/verif/black_box/int/simple_int_retr/no_t22
/t48/trunk/sw/verif/black_box/int/simple_jump_to/no_t21
/t48/trunk/sw/verif/black_box/int/simple_jump_to/no_t22
/t48/trunk/sw/verif/black_box/jbb/jbb_55/no_t21
/t48/trunk/sw/verif/black_box/jbb/jbb_55/no_t22
/t48/trunk/sw/verif/black_box/jbb/jbb_aa/no_t21
/t48/trunk/sw/verif/black_box/jbb/jbb_aa/no_t22
/t48/trunk/sw/verif/black_box/jbb/jbb_all_0/no_t21
/t48/trunk/sw/verif/black_box/jbb/jbb_all_0/no_t22
/t48/trunk/sw/verif/black_box/jbb/jbb_all_1/no_t21
/t48/trunk/sw/verif/black_box/jbb/jbb_all_1/no_t22
/t48/trunk/sw/verif/black_box/mb/call_jmp/no_t21
/t48/trunk/sw/verif/black_box/mb/call_jmp/no_t22
/t48/trunk/sw/verif/black_box/mb/int/no_t21
/t48/trunk/sw/verif/black_box/mb/int/no_t22
/t48/trunk/sw/verif/black_box/mcs2x
/t48/trunk/sw/verif/black_box/mov/ind_rr/no_t21
/t48/trunk/sw/verif/black_box/mov/ind_rr/no_t22
/t48/trunk/sw/verif/black_box/movp/no_t21
/t48/trunk/sw/verif/black_box/movp/no_t22
/t48/trunk/sw/verif/black_box/movx/no_t21
/t48/trunk/sw/verif/black_box/movx/no_t22
/t48/trunk/sw/verif/black_box/orl/bus/no_t21
/t48/trunk/sw/verif/black_box/orl/bus/no_t22
/t48/trunk/sw/verif/black_box/orl/pp/no_t21
/t48/trunk/sw/verif/black_box/orl/pp/no_t22
/t48/trunk/sw/verif/black_box/orl/rr/no_t21
/t48/trunk/sw/verif/black_box/orl/rr/no_t22
/t48/trunk/sw/verif/black_box/psw/no_t21
/t48/trunk/sw/verif/black_box/psw/no_t22
/t48/trunk/sw/verif/black_box/rb/int/no_t21
/t48/trunk/sw/verif/black_box/rb/int/no_t22
/t48/trunk/sw/verif/black_box/rb/misc/no_t21
/t48/trunk/sw/verif/black_box/rb/misc/no_t22
/t48/trunk/sw/verif/black_box/rc/no_t21
/t48/trunk/sw/verif/black_box/rc/no_t22
/t48/trunk/sw/verif/black_box/rl/no_t21
/t48/trunk/sw/verif/black_box/rl/no_t22
/t48/trunk/sw/verif/black_box/tim/int/no_t21
/t48/trunk/sw/verif/black_box/tx/t0/ent0_clk/no_t21
/t48/trunk/sw/verif/black_box/tx/t0/t0/no_t21
/t48/trunk/sw/verif/black_box/tx/t0/t0/test.asm
/t48/trunk/sw/verif/black_box/tx/t1/test.asm
/t48/trunk/sw/verif/black_box/upi41/basic_echo/no_t21
/t48/trunk/sw/verif/black_box/upi41/basic_echo/no_t22
/t48/trunk/sw/verif/black_box/upi41/basic_echo_int/no_t21
/t48/trunk/sw/verif/black_box/upi41/basic_echo_int/no_t22
/t48/trunk/sw/verif/black_box/upi41/dma/no_t21
/t48/trunk/sw/verif/black_box/upi41/dma/no_t22
/t48/trunk/sw/verif/black_box/upi41/master_int/no_t21
/t48/trunk/sw/verif/black_box/upi41/master_int/no_t22
/t48/trunk/sw/verif/black_box/upi41/status41a_test/no_t21
/t48/trunk/sw/verif/black_box/upi41/status41a_test/no_t22
/t48/trunk/sw/verif/black_box/upi41/status41_test/no_t21
/t48/trunk/sw/verif/black_box/upi41/status41_test/no_t22
/t48/trunk/sw/verif/black_box/xch/ind_rr/test.asm
/t48/trunk/sw/verif/black_box/xch/rr/no_t21
/t48/trunk/sw/verif/black_box/xch/rr/no_t22
/t48/trunk/sw/verif/black_box/xchd/test.asm
/t48/trunk/sw/verif/black_box/xrl/rr/no_t21
/t48/trunk/sw/verif/black_box/xrl/rr/no_t22
/t48/trunk/sw/verif/white_box/int_on_call/no_t21
/t48/trunk/sw/verif/white_box/int_on_call/no_t22
/t48/trunk/sw/verif/white_box/int_on_call/test.asm
/t48/trunk/sw/verif/white_box/int_on_jmp/no_t21
/t48/trunk/sw/verif/white_box/int_on_jmp/no_t22
/t48/trunk/sw/verif/white_box/int_on_jmp/test.asm
/t48/trunk/sw/verif/white_box/int_on_mb1/no_t21
/t48/trunk/sw/verif/white_box/int_on_mb1/no_t22
/t48/trunk/sw/verif/white_box/p1_port_reg_conflict/no_t21
/t48/trunk/sw/verif/white_box/p1_port_reg_conflict/no_t22
/t48/trunk/sw/verif/white_box/p2_io_exp/no_t21
/t48/trunk/sw/verif/white_box/p2_io_exp/no_t22
/t48/trunk/sw/verif/white_box/p2_port_reg_conflict/no_t21
/t48/trunk/sw/verif/white_box/p2_port_reg_conflict/no_t22
/t48/trunk/sw/verif/white_box/psen_rd_wr_timing/no_t21
/t48/trunk/sw/verif/white_box/psen_rd_wr_timing/no_t22
/t48/trunk/syn/t8022

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.