URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] - Rev 19

Path
/test_project/trunk/rtl/verilog/components/or1k_startup
/test_project/trunk/rtl/verilog/components/or1k_startup/copyright_OR1K_startup.v
/test_project/trunk/rtl/verilog/components/or1k_startup/copyright_spi.v
/test_project/trunk/rtl/verilog/components/or1k_startup/flash_wb_32x32.v
/test_project/trunk/rtl/verilog/components/or1k_startup/Makefile
/test_project/trunk/rtl/verilog/components/or1k_startup/OR1K_startup.v
/test_project/trunk/rtl/verilog/components/or1k_startup/OR1K_startup_ACTEL.v
/test_project/trunk/rtl/verilog/components/or1k_startup/OR1K_startup_ACTEL_IP.v
/test_project/trunk/rtl/verilog/components/or1k_startup/OR1K_startup_generic.v
/test_project/trunk/rtl/verilog/components/or1k_startup/OR1K_startup_module_inst.v
/test_project/trunk/rtl/verilog/components/or1k_startup/OR1K_startup_rom.v
/test_project/trunk/rtl/verilog/components/or1k_startup/spi_clgen.v
/test_project/trunk/rtl/verilog/components/or1k_startup/spi_defines.v
/test_project/trunk/rtl/verilog/components/or1k_startup/spi_flash.v
/test_project/trunk/rtl/verilog/components/or1k_startup/spi_shift.v
/test_project/trunk/rtl/verilog/components/or1k_startup/spi_top.v
/test_project/trunk/rtl/verilog/components/or1k_startup/timescale.v