URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] - Rev 42

Rev 42, 2009-05-06 19:45:47 GMT
Author: julius
Log message:
Fixed up to allow compilation with verilator. Mostly separation of modules into appropriate file names. However some vector declaration changes in the smii module has definitely broken it.

Path
/test_project/trunk/rtl/verilog/components/ethernet/eth_cop.v
/test_project/trunk/rtl/verilog/components/or1k_startup/spi_clgen.v
/test_project/trunk/rtl/verilog/components/or1k_startup/spi_flash.v
/test_project/trunk/rtl/verilog/components/or1k_startup/spi_flash_clgen.v
/test_project/trunk/rtl/verilog/components/or1k_startup/spi_flash_shift.v
/test_project/trunk/rtl/verilog/components/or1k_startup/spi_flash_top.v
/test_project/trunk/rtl/verilog/components/or1k_startup/spi_shift.v
/test_project/trunk/rtl/verilog/components/or1k_startup/spi_top.v
/test_project/trunk/rtl/verilog/components/or1k_top/or1k_top.v
/test_project/trunk/rtl/verilog/components/smii/smii_sync.v
/test_project/trunk/rtl/verilog/components/smii/smii_txrx.v
/test_project/trunk/rtl/verilog/components/uart16550/uart_transmitter.v
/test_project/trunk/rtl/verilog/components/wb_sdram_ctrl/fifo.v
/test_project/trunk/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl.v
/test_project/trunk/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_fifo.v
/test_project/trunk/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_top.v
/test_project/trunk/rtl/verilog/orpsoc_top.v
/test_project/trunk/sim/bin/icarus.scr
/test_project/trunk/sim/bin/Makefile