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Last modification

  • Rev 28, 2012-05-18 05:14:22 GMT
  • Author: earlz
  • Log message:
    Ok now registerfile is correct. Only using rising_edge. Now DataOut is the same as DataIn when WriteEnable is asserted.
    Some of my tests had to be changed because I was expecting the DataOut to be updated 1 clock cycle after the instruction rather than on the same clock cycle.
    Now it's truly single-cycle and without all the weird regIn stuff on the carryovers

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