URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] - Rev 50

Rev 50, 2001-12-06 14:51:10 GMT
Author: gorban
Log message:
Bug in LSR[0] is fixed.
All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.

Path
/trunk/rtl/verilog/uart_receiver.v
/trunk/rtl/verilog/uart_regs.v
/trunk/rtl/verilog/uart_top.v
/trunk/rtl/verilog/uart_wb.v
/trunk/sim/rtl_sim/bin/nc.scr