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URL https://opencores.org/ocsvn/xucpu/xucpu/trunk

Subversion Repositories xucpu

[/] - Rev 2

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Last modification

  • Rev 2, 2015-01-25 15:58:00 GMT
  • Author: lcdsgmtr
  • Log message:
    First checkin to make sure that the project does not get stale.
Path
/xucpu/trunk/COPYING
/xucpu/trunk/COPYING.LESSER
/xucpu/trunk/FPGA
/xucpu/trunk/FPGA/alu.vhdl
/xucpu/trunk/FPGA/alu2.vhdl
/xucpu/trunk/FPGA/clock.vhdl
/xucpu/trunk/FPGA/components.vhdl
/xucpu/trunk/FPGA/controllers.vhdl
/xucpu/trunk/FPGA/cpu.vhdl
/xucpu/trunk/FPGA/data_reg.vhdl
/xucpu/trunk/FPGA/decoder.vhdl
/xucpu/trunk/FPGA/gpio_in.vhdl
/xucpu/trunk/FPGA/gpio_out.vhdl
/xucpu/trunk/FPGA/incr.vhdl
/xucpu/trunk/FPGA/regf.vhdl
/xucpu/trunk/FPGA/startup_sim.vhdl
/xucpu/trunk/FPGA/sync_reset.vhdl
/xucpu/trunk/FPGA/system.vhdl
/xucpu/trunk/FPGA/system_package.vhdl
/xucpu/trunk/FPGA/system_sim.vhdl
/xucpu/trunk/FPGA/tty_in.vhdl
/xucpu/trunk/FPGA/tty_out.vhdl
/xucpu/trunk/FPGA/uart_clk.vhdl
/xucpu/trunk/FPGA/uctrl-init.vhdl
/xucpu/trunk/FPGA/uctrl-main.vhdl
/xucpu/trunk/FPGA/uctrl.vhdl
/xucpu/trunk/FPGA/zerof.vhdl
/xucpu/trunk/VHDL
/xucpu/trunk/VHDL/ALU
/xucpu/trunk/VHDL/ALU/ALU.vhdl
/xucpu/trunk/VHDL/bigrf
/xucpu/trunk/VHDL/bigrf/bigrf.vhdl
/xucpu/trunk/VHDL/blockram
/xucpu/trunk/VHDL/blockram/RAM.vhdl
/xucpu/trunk/VHDL/blockram/ram16x16_poc.vhdl
/xucpu/trunk/VHDL/blockram/tb_generic_ram.vhdl
/xucpu/trunk/VHDL/blockram/tb_large_ram.vhdl
/xucpu/trunk/VHDL/clock
/xucpu/trunk/VHDL/clock/clock.vhdl
/xucpu/trunk/VHDL/clock/test_clock.vhdl
/xucpu/trunk/VHDL/control
/xucpu/trunk/VHDL/control/ct.vhdl
/xucpu/trunk/VHDL/datapath
/xucpu/trunk/VHDL/datapath/datapath.vhdl
/xucpu/trunk/VHDL/datapath/dp_000.vhdl
/xucpu/trunk/VHDL/datapath/registers.vhdl
/xucpu/trunk/VHDL/datapath/tb_1.vhdl
/xucpu/trunk/VHDL/decoder
/xucpu/trunk/VHDL/decoder/decoder.vhdl
/xucpu/trunk/VHDL/file
/xucpu/trunk/VHDL/file/arrayio.vhdl
/xucpu/trunk/VHDL/file/file_reader.vhdl
/xucpu/trunk/VHDL/file/proc_reader.vhdl
/xucpu/trunk/VHDL/file/sign_reader.vhdl
/xucpu/trunk/VHDL/FSMII
/xucpu/trunk/VHDL/FSMII/fsm.vhdl
/xucpu/trunk/VHDL/issue_01
/xucpu/trunk/VHDL/issue_01/array_issue.vhdl
/xucpu/trunk/VHDL/issue_01/array_issue_03.vhdl
/xucpu/trunk/VHDL/issue_01/array_issue_2.vhdl
/xucpu/trunk/VHDL/issue_02
/xucpu/trunk/VHDL/issue_02/string_issue.vhdl
/xucpu/trunk/VHDL/large_ram
/xucpu/trunk/VHDL/large_ram/RAM4kx16.vhdl
/xucpu/trunk/VHDL/large_ram/RAM32kx16.vhdl
/xucpu/trunk/VHDL/multiplexer
/xucpu/trunk/VHDL/multiplexer/MUX.vhdl
/xucpu/trunk/VHDL/mux2to1
/xucpu/trunk/VHDL/mux2to1/mux2to1.vhdl
/xucpu/trunk/VHDL/mux4to1
/xucpu/trunk/VHDL/mux4to1/mux4to1.vhdl
/xucpu/trunk/VHDL/mux8to1
/xucpu/trunk/VHDL/mux8to1/mux4to1.vhdl
/xucpu/trunk/VHDL/pipeline
/xucpu/trunk/VHDL/pipeline/adder.vhdl
/xucpu/trunk/VHDL/pipeline/clock.vhdl
/xucpu/trunk/VHDL/pipeline/memory.vhdl
/xucpu/trunk/VHDL/pipeline/memory_controller-arch.vhdl
/xucpu/trunk/VHDL/pipeline/memory_controller-mealy.vhdl
/xucpu/trunk/VHDL/pipeline/memory_controller.vhdl
/xucpu/trunk/VHDL/pipeline/memory_pipeline.vhdl
/xucpu/trunk/VHDL/pipeline/memory_processor-arch.vhdl
/xucpu/trunk/VHDL/pipeline/memory_processor-mealy.vhdl
/xucpu/trunk/VHDL/pipeline/memory_processor.vhdl
/xucpu/trunk/VHDL/pipeline/mux.vhdl
/xucpu/trunk/VHDL/pipeline/pipeline_controller-arch.vhdl
/xucpu/trunk/VHDL/pipeline/pipeline_controller-mealy.vhdl
/xucpu/trunk/VHDL/pipeline/pipeline_controller-moore.vhdl
/xucpu/trunk/VHDL/pipeline/pipeline_controller-rofsm.vhdl
/xucpu/trunk/VHDL/pipeline/pipeline_controller.vhdl
/xucpu/trunk/VHDL/pipeline/pipeline_reg.vhdl
/xucpu/trunk/VHDL/pipeline/processor-arch.vhdl
/xucpu/trunk/VHDL/pipeline/processor-mealy.vhdl
/xucpu/trunk/VHDL/pipeline/processor-moore.vhdl
/xucpu/trunk/VHDL/pipeline/processor-rofsm.vhdl
/xucpu/trunk/VHDL/pipeline/processor.vhdl
/xucpu/trunk/VHDL/pipeline/reset.vhdl
/xucpu/trunk/VHDL/pipeline/test_pipeline.vhdl
/xucpu/trunk/VHDL/qctrl
/xucpu/trunk/VHDL/qctrl/t_qctrl.vhdl
/xucpu/trunk/VHDL/qreg
/xucpu/trunk/VHDL/qreg/qreg.vhdl
/xucpu/trunk/VHDL/queue
/xucpu/trunk/VHDL/queue/queue.vhdl
/xucpu/trunk/VHDL/queue_2
/xucpu/trunk/VHDL/queue_2/queue.vhdl
/xucpu/trunk/VHDL/queue_2/tb_prod_cons.vhdl
/xucpu/trunk/VHDL/queue_2/test_queue.vhdl
/xucpu/trunk/VHDL/registers
/xucpu/trunk/VHDL/registers/alu.vhdl
/xucpu/trunk/VHDL/registers/clock.vhdl
/xucpu/trunk/VHDL/registers/control.vhdl
/xucpu/trunk/VHDL/registers/mux.vhdl
/xucpu/trunk/VHDL/registers/pipeline_reg.vhdl
/xucpu/trunk/VHDL/registers/register_test.vhdl
/xucpu/trunk/VHDL/registers/reset.vhdl
/xucpu/trunk/VHDL/registers/rf.vhdl
/xucpu/trunk/VHDL/ROM
/xucpu/trunk/VHDL/ROM/ROM.vhdl
/xucpu/trunk/VHDL/ROM/tb_rom.vhdl
/xucpu/trunk/VHDL/rtl_alu
/xucpu/trunk/VHDL/rtl_alu/boole.vhdl
/xucpu/trunk/VHDL/shift
/xucpu/trunk/VHDL/shift/shift.vhdl
/xucpu/trunk/VHDL/speed
/xucpu/trunk/VHDL/speed/flipflop.vhdl
/xucpu/trunk/VHDL/speed/tb_flipflop.vhdl
/xucpu/trunk/VHDL/uCtrl
/xucpu/trunk/VHDL/uCtrl/ROM1.vhdl
/xucpu/trunk/VHDL/uCtrl/tb_rom.vhdl
/xucpu/trunk/VHDL/uCtrl/test_rom.vhdl

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