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Last modification

  • Rev 83, 2016-01-02 23:51:37 GMT
  • Author: dgisselq
  • Log message:
    Added a flag to indicate whether an exception took place on the first
    or second half of a VLIW instruction--will be zero in non-VLIW mode,
    equivalent to the second half of the instruction having caused the
    exception. (Expect these flags to be reordered some time in the future into
    a less haphazard ordering ...)

    Vastly simplified the pipeline logic, primarily for op_stall, but also touched
    opA and opB. (Trying to fit within timing on Spartan 6 ...)

    Changed division instruction to include a reset on clear_pipeline, to make
    certain [BC $addr; DIV Rx,Ry ] works regardless of whether the condition is

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