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I/O read timing

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Information:
Type :: BUG
Status :: OPENED
Assigned to :: nobody

Description:
Hi Goran,
Firstly, congratulations for the superb job you’ve done in creating this model and thanks for all your hard work.

I’ve been using the A-Z80 core in a Xilinx FPGA to replace a Z80 in a Cambridge Z88 and unfortunately it didn’t work initially. I eventually tracked the problem down to the timing of the I/O read instructions (in a,(c) in this case). The read latch enable signal (SYNTHESIZED_WIRE_2 in data_pins.v) becomes active during the TW cycle of the I/O read instructions, thus latching the data in the middle of the instruction rather than at the end as the real Z80 does. This is a problem for the Z88 hardware since the read data is not stable at this time.

I have verified that this is the cause of my problem by delaying the read enable signal (bus_db_pin_re in z80_top_direct_n.v) by 1 clock cycle when nIORQ is low so that it is active during the T3 clock cycle. With this modification the core works perfectly with the Z88 hardware even putting the contents of the I register onto the address bus during halt, which other models I tried did not. This feature is used by the Z88 to detect key presses while “asleep”.
Martin

Comments:

Devic, Goran Feb 4, 2019
Thank you, Martin, I understand the basic idea of your workaround. I will check against more simulations and upload a fix. Regards,
Devic, Goran Feb 3, 2019
Hi Martin, thank you for the feedback!

Do you have changes that could be pushed to the sources? If so, could you push them to a mirror here "https://github.com/gdevic/A-Z80"?

Best Regards, Goran
Wolak, Michael Feb 3, 2019
Wolak, Michael Feb 3, 2019
, Feb 3, 2019
mmm, that didn't come out quite right when I pasted it, should be dre sorry

, Feb 3, 2019
Hi Goran,

I just did a quick fix at the top level to verify the cause of the problem. It’s probably best if someone with an in-depth knowledge of the internals provides a proper solution. This is what I did in z80_top_direct_n.v...

// delay read enable
reg dre;
wire sdre;
always @(posedge clk) begin
dre end
// use delayed signal for I/O reads only
assign sdre = nIORQ ? bus_db_pin_re : dre;

data_pins data_pins_(
.bus_db_pin_oe (bus_db_pin_oe),
.bus_db_pin_re (sdre), // pass selected signal to data latches
.ctl_bus_db_we (ctl_bus_db_we),
.ctl_bus_db_oe (ctl_bus_db_oe),
.clk (clk),
.db (db0),
.D (D)
);

Hope this is of some use,
best regards,
Martin
Type your text here
Devic, Goran Feb 3, 2019
Hi Martin, thank you for the feedback!

Do you have changes that could be pushed to the sources? If so, could you push them to a mirror here "https://github.com/gdevic/A-Z80"?

Best Regards, Goran

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