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Name: a-z80
Created: Dec 12, 2014
Updated: Sep 10, 2020
SVN Updated: Jul 12, 2020
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 4 reported / 2 solved
Star29you like it: star it!

Other project properties

Development status:Stable
Additional info:Design done, FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: LGPL


Update: Rewritten in pure Verilog, the CPU can now be used on both Altera and Xilinx devices!

A-Z80 is a conceptual implementation of the venerable Zilog Z80 processor targeted to synthesize and run on a modern FPGA device. It differs from the existing (mostly Verilog) Z80 implementations in that it is designed from the ground-up through the schematics and low-level gates. It is a result of a research and tedious reverse-engineering of Z80 at all levels, including micro-photographs of a die.

A-Z80 CPU Top-level

Project includes a fully working Sinclair ZX Spectrum implementation based on this CPU.
It has been described in more details at BaltazarStudios.


  • Cycle and bus accurate including the correct behavior of nWAIT and nBUSRQ
  • All documented and undocumented opcodes, flags and registers, including R, WZ
  • Following the actual arcitectural model down to the individual gates and registers for some modules
  • Passes ZEXDOC and ZEXLL (except quirky OTIR/LDIR for IX,IY)
  • Correct behavior of BIT n,(HL) to expose WZ
  • All interrupts modes (IM0,IM1,IM2)
  • Slow Model fMax is 18 MHz, could be run even faster when optimized

Playing Mainc Miner on A-Z80 based ZX Spectrum implementation:

Manic Miner


A Quick Start document is here: View

Complete User's Guide is here: View

In addition, project files contain a number of readme's to help you understand, recreate it and/or add A-Z80 to your own project.


RTL Simulation

Design is simulated using ModelSim.

  • Each module contains a ModelSim project
  • Contain individual SystemVerilog test files
  • Test wave (*.do) files to quickly set up views

Framework is also developed around the Fuse tests (low-level Z80 CPU) that run each Z80 instruction on the ModelSim and automatically compare to the expected Fuse test result files. Mis-matches are flagged.

There is a "quick" sanity test as well as a much longer comprehensive test.

Top-level Simulation

ZMAC assember is used to generate Z80 program test snippets which are then run in the simulation and on the actual FPGA hardware. The resulting files should match.
This level of tests adds UART to the ModelSim and FPGA implementation so the tests can be run and outputs compared.

Tests include:

  • Tests for various complex instructions like DAA, NEG
  • Classic "Hello, World" application
  • Tests for interrupt behavior
  • ...and more tests embedded in *.asm test files


Several complete and working FPGA designs illustrate implementation and test the A-Z80 on both Altera and Xilinx devices:

  • Basic Computer using keyboard and UART to run Z80 tests
  • Complete implementation of a Sinclair ZX Spectrum

Running ZEXDOC and ZEXALL tests on a Basic Computer implementation:



This design is fully completed, tested and working.

A Cyclone II based Altera DE1 board implementation used about 11% of its LE's.

Compiled size

A Spartan-6 based Nexys3 board implementation used about 19% of its slices.

Compiled size

This implementation is using free Altera and Xilinx tools (Quartus II v13.0.1 Web Edition and Xilinx ISE Webpack). It also uses Python 3.5 to build some components and tests.
Although based on Altera and Xilinx devices, this project could be used with other vendors since (Quartus-specific) schematic files are pre-compiled into generic Verilog files.