Update: Rewritten in pure Verilog, the CPU can now be used on both Altera and Xilinx devices!
A-Z80 is a conceptual implementation of the venerable Zilog Z80 processor targeted to synthesize and run on a modern FPGA device. It differs from the existing (mostly Verilog) Z80 implementations in that it is designed from the ground-up through the schematics and low-level gates. It is a result of a research and tedious reverse-engineering of Z80 at all levels, including micro-photographs of a die.
Project includes a fully working Sinclair ZX Spectrum implementation based on this CPU.
It has been described in more details at BaltazarStudios.
Playing Mainc Miner on A-Z80 based ZX Spectrum implementation:
A Quick Start document is here: View
Complete User's Guide is here: View
In addition, project files contain a number of readme's to help you understand, recreate it and/or add A-Z80 to your own project.
Design is simulated using ModelSim.
Framework is also developed around the Fuse tests (low-level Z80 CPU) that run each Z80 instruction on the ModelSim and automatically compare to the expected Fuse test result files. Mis-matches are flagged.
There is a "quick" sanity test as well as a much longer comprehensive test.
ZMAC assember is used to generate Z80 program test snippets which are then run in the simulation and on the actual FPGA hardware. The resulting files should match.
This level of tests adds UART to the ModelSim and FPGA implementation so the tests can be run and outputs compared.
Several complete and working FPGA designs illustrate implementation and test the A-Z80 on both Altera and Xilinx devices:
Running ZEXDOC and ZEXALL tests on a Basic Computer implementation:
This design is fully completed, tested and working.
A Cyclone II based Altera DE1 board implementation used about 11% of its LE's.
A Spartan-6 based Nexys3 board implementation used about 19% of its slices.
This implementation is using free Altera and Xilinx tools (Quartus II v13.0.1 Web Edition and Xilinx ISE Webpack). It also uses Python 3.5 to build some components and tests.
Although based on Altera and Xilinx devices, this project could be used with other vendors since (Quartus-specific) schematic files are pre-compiled into generic Verilog files.