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Verilog "Task" Help
by UmairSiddiqui on Apr 16, 2007 |
UmairSiddiqui
Posts: 21 Joined: Aug 13, 2005 Last seen: Sep 19, 2016 |
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/**** given code sample doesn't make sense but any ways ***/
module Controller
(
input clk,
output reg wb_dat_o
);
always begin
wb_write(clk);
end
task wb_write;
input a;
begin
wb_dat_o = a;
end
endtask
/* OR */
always begin
wb_write;
end
task wb_write;
begin
wb_dat_o = clk;
end
endtask
endmodule
On 4/16/07, DigitalHomeSoutions at cox.net DigitalHomeSoutions at cox.net> wrote:
Help! I've tried everything I can think of to try and get the
Verilog "Task" function to work with ISE but I keep getting errors that
Xilinx is working on the issue or the service pack has the fix (didn't
work).
Can anyone tell me what the correct format is for using the "Task"
function in ISE? Here is what I have so far:
module Controller(
input clk,
output reg wb_dat_o);
always begin
wb_write(clk, wb_dat_o);
end
task wb_write;
input a;
output reg out;
assign out = a;
endtask
endmodule
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
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Verilog "Task" Help
by Unknown on Apr 16, 2007 |
Not available! | ||
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Help! I've tried everything I can think of to try and get the
Verilog "Task" function to work with ISE but I keep getting errors that Xilinx is working on the issue or the service pack has the fix (didn't work). Can anyone tell me what the correct format is for using the "Task" function in ISE? Here is what I have so far: module Controller( input clk, output reg wb_dat_o); always begin wb_write(clk, wb_dat_o); end task wb_write; input a; output reg out; assign out = a; endtask endmodule |
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Verilog "Task" Help
by Unknown on Apr 16, 2007 |
Not available! | ||
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On 4/16/07, DigitalHomeSoutions at cox.net DigitalHomeSoutions at cox.net> wrote:
Help! I've tried everything I can think of to try and get the Verilog "Task" function to work with ISE but I keep getting errors that Xilinx is working on the issue or the service pack has the fix (didn't work). Can anyone tell me what the correct format is for using the "Task" function in ISE? Here is what I have so far: module Controller( input clk, output reg wb_dat_o); always begin wb_write(clk, wb_dat_o); end Synthesizable blocks need a sensitivity list: always @(posedge clk) begin wr_write (clk, wb_dat_o); end task wb_write;
input a;
output reg out; assign out = a; Assign statements are only valid on wires, and only valid outside of a block. Also missing begin/end statements. Task outputs are implied 'reg', it does not need to be declared. task wb_write; input a; output out; begin out = a; end endtask endtask
endmodule
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
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