OpenCores

OpenCores

Question on Ethernet MAC 10/100 Mbps

no use

no use

1/2

Next

Last

Question on Ethernet MAC 10/100 Mbps by Unknown on May 2, 2007			Not available!
Haven't looked at the 10/100 MAC, but there seem to be some basic confusion here about Ethernet. On 5/2/07, <A HREF="http://www.opencores.org/mailman/listinfo/cores">yeuchaucheng at gmail.com</A> <<A HREF="http://www.opencores.org/mailman/listinfo/cores">yeuchaucheng at gmail.com</A>> wrote: [q] I really need help on this IP Core. [q]>From what I understand, The data we transmit from phy are store in the[/q] MiiM register called PRSD.[/q] MIIM = MII management If this is really an MIIM register, it's a control interface to the PHY and not a data interface. MIIM typically used to read/write PHY parameters. If, as it sounds, you're trying to use the core to do packet injection, you should probably do it the obvious way: create a side buffer, load the data you want to inject into the buffer, put a mux between your side buffer and the main datapath, and use the normal data interface to the MAC to inject your traffic. -------------- next part -------------- An HTML attachment was scrubbed... URL: <A HREF="http://www.opencores.org/forums.cgi/cores/attachments/20070502/44acb1e6/attachment.htm">http://www.opencores.org/forums.cgi/cores/attachments/20070502/44acb1e6/attachment.htm</A> Haven't looked at the 10/100 MAC, but there seem to be some basic confusion here about Ethernet. On 5/2/07, yeuchaucheng at gmail.com yeuchaucheng at gmail.com> wrote: I really need help on this IP Core. >From what I understand, The data we transmit from phy are store in the MiiM register called PRSD. MIIM = MII management If this is really an MIIM register, it's a control interface to the PHY and not a data interface. MIIM typically used to read/write PHY parameters. If, as it sounds, you're trying to use the core to do packet injection, you should probably do it the obvious way: create a side buffer, load the data you want to inject into the buffer, put a mux between your side buffer and the main datapath, and use the normal data interface to the MAC to inject your traffic. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20070502/44acb1e6/attachment.htm

Question on Ethernet MAC 10/100 Mbps by Unknown on May 2, 2007			Not available!
I really need help on this IP Core. [q]From what I understand, The data we transmit from phy are store in the [/q] MiiM register called PRSD. I want to know how exactly can we load the data into PRSD. I've look into schematics of the core, and look what gates are involved in sending data to PRSD, I created a testbench waveform, and tried to set all the values to see if I was able to communicated with PRSD. But I've had no luck but errors. what I am trying to do is this, I want to load a string of data across ethernet core. say if I have a request, and I want to load the request through the ethernet core to the Host interface. I was not able to figure how to do that. Also, I tried the test bench, but it's giving a lot of random errors, lately I've been receiving this error "Verilog tasks/functions with fork-Join constructs are unsupported. Codegen failed for module "tb_ethernet"" I want to know how do we use test bench to test so that it will allow the data to store in PRSD register and pass it on to Host Interface. I don't know if this is clear to you, or if it's confusing. But I am doing a project where I send a request through ethernet core, and store it in external memory, so that the request can be processed further. So, I need to know how to transmit the request so that it can be transmit thru the Host Interface. I would really appreciate if you can help me on that, becasuse I've been stuck on it, and couldn't go any further with my project thanks, Michael I really need help on this IP Core. From what I understand, The data we transmit from phy are store in the MiiM register called PRSD. I want to know how exactly can we load the data into PRSD. I've look into schematics of the core, and look what gates are involved in sending data to PRSD, I created a testbench waveform, and tried to set all the values to see if I was able to communicated with PRSD. But I've had no luck but errors. what I am trying to do is this, I want to load a string of data across ethernet core. say if I have a request, and I want to load the request through the ethernet core to the Host interface. I was not able to figure how to do that. Also, I tried the test bench, but it's giving a lot of random errors, lately I've been receiving this error "Verilog tasks/functions with fork-Join constructs are unsupported. Codegen failed for module "tb_ethernet"" I want to know how do we use test bench to test so that it will allow the data to store in PRSD register and pass it on to Host Interface. I don't know if this is clear to you, or if it's confusing. But I am doing a project where I send a request through ethernet core, and store it in external memory, so that the request can be processed further. So, I need to know how to transmit the request so that it can be transmit thru the Host Interface. I would really appreciate if you can help me on that, becasuse I've been stuck on it, and couldn't go any further with my project thanks, Michael

Question on Ethernet MAC 10/100 Mbps by Unknown on May 3, 2007			Not available!
what confusion are you refering to?? ----- Original Message ----- From: Guy Hutchison<<A HREF="http://www.opencores.org/mailman/listinfo/cores">ghutchis at g...</A>> To: Date: Wed May 2 07:43:16 CEST 2007 Subject: [oc] Question on Ethernet MAC 10/100 Mbps [q] Haven't looked at the 10/100 MAC, but there seem to be some basic confusion here about Ethernet. On 5/2/07, attachment.html [/q] what confusion are you refering to?? ----- Original Message ----- From: Guy Hutchisonghutchis at g...> To: Date: Wed May 2 07:43:16 CEST 2007 Subject: [oc] Question on Ethernet MAC 10/100 Mbps Haven't looked at the 10/100 MAC, but there seem to be some basic confusion here about Ethernet. On 5/2/07, attachment.html

Question on Ethernet MAC 10/100 Mbps by Unknown on May 3, 2007			Not available!
anyone can help me on this I really need the help to get the data across from phy to host interface thanks ----- Original Message ----- From: yeuchaucheng at gmail.com<<A HREF="http://www.opencores.org/mailman/listinfo/cores">yeuchaucheng at g...</A>> To: Date: Wed May 2 10:30:01 CEST 2007 Subject: [oc] Question on Ethernet MAC 10/100 Mbps [q] I really need help on this IP Core. [q]>From what I understand, The data we transmit from phy are store [/q] in the MiiM register called PRSD. I want to know how exactly can we load the data into PRSD. I've look into schematics of the core, and look what gates are involved in sending data to PRSD, I created a testbench waveform, and tried to set all the values to see if I was able to communicated with PRSD. But I've had no luck but errors. what I am trying to do is this, I want to load a string of data across ethernet core. say if I have a request, and I want to load the request through the ethernet core to the Host interface. I was not able to figure how to do that. Also, I tried the test bench, but it's giving a lot of random errors, lately I've been receiving this error "Verilog tasks/functions with fork-Join constructs are unsupported. Codegen failed for module "tb_ethernet"" I want to know how do we use test bench to test so that it will allow the data to store in PRSD register and pass it on to Host Interface. I don't know if this is clear to you, or if it's confusing. But I am doing a project where I send a request through ethernet core, and store it in external memory, so that the request can be processed further. So, I need to know how to transmit the request so that it can be transmit thru the Host Interface. I would really appreciate if you can help me on that, becasuse I've been stuck on it, and couldn't go any further with my project thanks, Michael [/q] anyone can help me on this I really need the help to get the data across from phy to host interface thanks ----- Original Message ----- From: yeuchaucheng at gmail.comyeuchaucheng at g...> To: Date: Wed May 2 10:30:01 CEST 2007 Subject: [oc] Question on Ethernet MAC 10/100 Mbps I really need help on this IP Core. >From what I understand, The data we transmit from phy are store in the MiiM register called PRSD. I want to know how exactly can we load the data into PRSD. I've look into schematics of the core, and look what gates are involved in sending data to PRSD, I created a testbench waveform, and tried to set all the values to see if I was able to communicated with PRSD. But I've had no luck but errors. what I am trying to do is this, I want to load a string of data across ethernet core. say if I have a request, and I want to load the request through the ethernet core to the Host interface. I was not able to figure how to do that. Also, I tried the test bench, but it's giving a lot of random errors, lately I've been receiving this error "Verilog tasks/functions with fork-Join constructs are unsupported. Codegen failed for module "tb_ethernet"" I want to know how do we use test bench to test so that it will allow the data to store in PRSD register and pass it on to Host Interface. I don't know if this is clear to you, or if it's confusing. But I am doing a project where I send a request through ethernet core, and store it in external memory, so that the request can be processed further. So, I need to know how to transmit the request so that it can be transmit thru the Host Interface. I would really appreciate if you can help me on that, becasuse I've been stuck on it, and couldn't go any further with my project thanks, Michael

Question on Ethernet MAC 10/100 Mbps by Unknown on May 7, 2007			Not available!
I also wander what confusion is in the Ethernet MAC. If you want to transfer data between the host CPU and PHY, you should use the MIIM interface. It is well described in the 802.3 specification and each PHY specification. All those that used Ethernet MAC IP Core, used it to configure the PHY and it is working fine. Regards, Igor Mohor On 5/3/07, <A HREF="http://www.opencores.org/mailman/listinfo/cores">yeuchaucheng at gmail.com</A> <<A HREF="http://www.opencores.org/mailman/listinfo/cores">yeuchaucheng at gmail.com</A>> wrote: [q] anyone can help me on this I really need the help to get the data across from phy to host interface thanks ----- Original Message ----- From: yeuchaucheng at gmail.com<<A HREF="http://www.opencores.org/mailman/listinfo/cores">yeuchaucheng at g...</A>> To: Date: Wed May 2 10:30:01 CEST 2007 Subject: [oc] Question on Ethernet MAC 10/100 Mbps [q]> I really need help on this IP Core. [q] >From what I understand, The data we transmit from phy are store[/q] > in the > MiiM register called PRSD. > > I want to know how exactly can we load the data into PRSD. > I've look into schematics of the core, and look what gates are > involved > in sending data to PRSD, I created a testbench waveform, and tried > to > set all the values to see if I was able to communicated with PRSD. > But > I've had no luck but errors. > > what I am trying to do is this, I want to load a string of data > across > ethernet core. > say if I have a request, and I want to load the request through the > ethernet core to the Host interface. > I was not able to figure how to do that. > > Also, I tried the test bench, but it's giving a lot of random > errors, lately > I've been receiving this error "Verilog tasks/functions with > fork-Join > constructs are unsupported. > Codegen failed for module "tb_ethernet"" > I want to know how do we use test bench to test so that it will > allow > the data to store in PRSD register and pass it on to Host > Interface. > > I don't know if this is clear to you, or if it's confusing. > But I am doing a project where I send a request through ethernet > core, > and store it in external memory, so that the request can be > processed > further. > So, I need to know how to transmit the request so that it can be > transmit thru the Host Interface. > > > I would really appreciate if you can help me on that, becasuse I've > been > stuck on it, and couldn't go any further with my project > > thanks, > > Michael > >[/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] -------------- next part -------------- An HTML attachment was scrubbed... URL: <A HREF="http://www.opencores.org/forums.cgi/cores/attachments/20070507/c17f618a/attachment.htm">http://www.opencores.org/forums.cgi/cores/attachments/20070507/c17f618a/attachment.htm</A> I also wander what confusion is in the Ethernet MAC. If you want to transfer data between the host CPU and PHY, you should use the MIIM interface. It is well described in the 802.3 specification and each PHY specification. All those that used Ethernet MAC IP Core, used it to configure the PHY and it is working fine. Regards, Igor Mohor On 5/3/07, yeuchaucheng at gmail.com yeuchaucheng at gmail.com> wrote: anyone can help me on this I really need the help to get the data across from phy to host interface thanks ----- Original Message ----- From: yeuchaucheng at gmail.comyeuchaucheng at g...> To: Date: Wed May 2 10:30:01 CEST 2007 Subject: [oc] Question on Ethernet MAC 10/100 Mbps > I really need help on this IP Core. >From what I understand, The data we transmit from phy are store > in the > MiiM register called PRSD. > > I want to know how exactly can we load the data into PRSD. > I've look into schematics of the core, and look what gates are > involved > in sending data to PRSD, I created a testbench waveform, and tried > to > set all the values to see if I was able to communicated with PRSD. > But > I've had no luck but errors. > > what I am trying to do is this, I want to load a string of data > across > ethernet core. > say if I have a request, and I want to load the request through the > ethernet core to the Host interface. > I was not able to figure how to do that. > > Also, I tried the test bench, but it's giving a lot of random > errors, lately > I've been receiving this error "Verilog tasks/functions with > fork-Join > constructs are unsupported. > Codegen failed for module "tb_ethernet"" > I want to know how do we use test bench to test so that it will > allow > the data to store in PRSD register and pass it on to Host > Interface. > > I don't know if this is clear to you, or if it's confusing. > But I am doing a project where I send a request through ethernet > core, > and store it in external memory, so that the request can be > processed > further. > So, I need to know how to transmit the request so that it can be > transmit thru the Host Interface. > > > I would really appreciate if you can help me on that, becasuse I've > been > stuck on it, and couldn't go any further with my project > > thanks, > > Michael > > _______________________________________________ http://www.opencores.org/mailman/listinfo/cores -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20070507/c17f618a/attachment.htm

Question on Ethernet MAC 10/100 Mbps by Unknown on May 7, 2007			Not available!
It's possible that I'm confused instead. In the designes I've worked on, MIIM = MII Management, which is the little 2-wire interface that the MAC uses to talk to the PHY. It's used to configure the PHY, it's not used to try and get the PHY to send specific data packets. However, the original poster may have meant that MIIM = MII Media, which would be the data interface between MAC and PHY. How I read the original post was that the poster wanted to push data in through the host CPU interface to get the MAC to send some special CPU-defined packet. I guess the other way to read it is that he wanted to send info through the host data interface, which of course would be the right way to do things. - Guy On 5/7/07, Igor Mohor <<A HREF="http://www.opencores.org/mailman/listinfo/cores">igor.mohor at gmail.com</A>> wrote: [q] I also wander what confusion is in the Ethernet MAC. If you want to transfer data between the host CPU and PHY, you should use the MIIM interface. It is well described in the 802.3 specification and each PHY specification. All those that used Ethernet MAC IP Core, used it to configure the PHY and it is working fine. Regards, Igor Mohor On 5/3/07, <A HREF="http://www.opencores.org/mailman/listinfo/cores">yeuchaucheng at gmail.com</A> < <A HREF="http://www.opencores.org/mailman/listinfo/cores">yeuchaucheng at gmail.com</A>> wrote: [q]> > anyone can help me on this > I really need the help to get the data across from phy to host interface > > > thanks > > ----- Original Message ----- > From: yeuchaucheng at gmail.com<<A HREF="http://www.opencores.org/mailman/listinfo/cores">yeuchaucheng at g...</A>> > To: > Date: Wed May 2 10:30:01 CEST 2007 > Subject: [oc] Question on Ethernet MAC 10/100 Mbps > [q] > I really need help on this IP Core. [q]> >From what I understand, The data we transmit from phy are store[/q] > in the > MiiM register called PRSD. > > I want to know how exactly can we load the data into PRSD. > I've look into schematics of the core, and look what gates are > involved > in sending data to PRSD, I created a testbench waveform, and tried > to > set all the values to see if I was able to communicated with PRSD. > But > I've had no luck but errors. > > what I am trying to do is this, I want to load a string of data > across > ethernet core. > say if I have a request, and I want to load the request through the > ethernet core to the Host interface. > I was not able to figure how to do that. > > Also, I tried the test bench, but it's giving a lot of random > errors, lately > I've been receiving this error "Verilog tasks/functions with > fork-Join > constructs are unsupported. > Codegen failed for module "tb_ethernet"" > I want to know how do we use test bench to test so that it will > allow > the data to store in PRSD register and pass it on to Host > Interface. > > I don't know if this is clear to you, or if it's confusing. > But I am doing a project where I send a request through ethernet > core, > and store it in external memory, so that the request can be > processed > further. > So, I need to know how to transmit the request so that it can be > transmit thru the Host Interface. > > > I would really appreciate if you can help me on that, becasuse I've > been > stuck on it, and couldn't go any further with my project > > thanks, > > Michael > >[/q] > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> >[/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] -------------- next part -------------- An HTML attachment was scrubbed... URL: <A HREF="http://www.opencores.org/forums.cgi/cores/attachments/20070507/a4070667/attachment.htm">http://www.opencores.org/forums.cgi/cores/attachments/20070507/a4070667/attachment.htm</A> It's possible that I'm confused instead. In the designes I've worked on, MIIM = MII Management, which is the little 2-wire interface that the MAC uses to talk to the PHY. It's used to configure the PHY, it's not used to try and get the PHY to send specific data packets. However, the original poster may have meant that MIIM = MII Media, which would be the data interface between MAC and PHY. How I read the original post was that the poster wanted to push data in through the host CPU interface to get the MAC to send some special CPU-defined packet. I guess the other way to read it is that he wanted to send info through the host data interface, which of course would be the right way to do things. - Guy On 5/7/07, Igor Mohor igor.mohor at gmail.com> wrote: I also wander what confusion is in the Ethernet MAC. If you want to transfer data between the host CPU and PHY, you should use the MIIM interface. It is well described in the 802.3 specification and each PHY specification. All those that used Ethernet MAC IP Core, used it to configure the PHY and it is working fine. Regards, Igor Mohor On 5/3/07, yeuchaucheng at gmail.com yeuchaucheng at gmail.com> wrote: > > anyone can help me on this > I really need the help to get the data across from phy to host interface > > > thanks > > ----- Original Message ----- > From: yeuchaucheng at gmail.comyeuchaucheng at g...> > To: > Date: Wed May 2 10:30:01 CEST 2007 > Subject: [oc] Question on Ethernet MAC 10/100 Mbps > > I really need help on this IP Core. > >From what I understand, The data we transmit from phy are store > in the > MiiM register called PRSD. > > I want to know how exactly can we load the data into PRSD. > I've look into schematics of the core, and look what gates are > involved > in sending data to PRSD, I created a testbench waveform, and tried > to > set all the values to see if I was able to communicated with PRSD. > But > I've had no luck but errors. > > what I am trying to do is this, I want to load a string of data > across > ethernet core. > say if I have a request, and I want to load the request through the > ethernet core to the Host interface. > I was not able to figure how to do that. > > Also, I tried the test bench, but it's giving a lot of random > errors, lately > I've been receiving this error "Verilog tasks/functions with > fork-Join > constructs are unsupported. > Codegen failed for module "tb_ethernet"" > I want to know how do we use test bench to test so that it will > allow > the data to store in PRSD register and pass it on to Host > Interface. > > I don't know if this is clear to you, or if it's confusing. > But I am doing a project where I send a request through ethernet > core, > and store it in external memory, so that the request can be > processed > further. > So, I need to know how to transmit the request so that it can be > transmit thru the Host Interface. > > > I would really appreciate if you can help me on that, becasuse I've > been > stuck on it, and couldn't go any further with my project > > thanks, > > Michael > > > _______________________________________________ > http://www.opencores.org/mailman/listinfo/cores > _______________________________________________ http://www.opencores.org/mailman/listinfo/cores -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20070507/a4070667/attachment.htm

Question on Ethernet MAC 10/100 Mbps by Unknown on May 10, 2007			Not available!
basically I want to send a data from phy to Host interface, which will be an external memory. I am pretty new to this, and I've read the specs of ethernet mac core, but that didn't help me much. I don't know what exactly needs to be configured, and the test bench has so many bugs in it, it's been giving me error even without changing anything in test bench. hope what I want to do is clear to you thanks, Michael ----- Original Message ----- From: Igor Mohor<<A HREF="http://www.opencores.org/mailman/listinfo/cores">igor.mohor at g...</A>> To: Date: Mon May 7 10:23:45 CEST 2007 Subject: [oc] Question on Ethernet MAC 10/100 Mbps [q] I also wander what confusion is in the Ethernet MAC. If you want to transfer data between the host CPU and PHY, you should use the MIIM interface. It is well described in the 802.3 specification and each PHY specification. All those that used Ethernet MAC IP Core, used it to configure the PHY and it is working fine. Regards, Igor Mohor On 5/3/07, attachment.html [/q] basically I want to send a data from phy to Host interface, which will be an external memory. I am pretty new to this, and I've read the specs of ethernet mac core, but that didn't help me much. I don't know what exactly needs to be configured, and the test bench has so many bugs in it, it's been giving me error even without changing anything in test bench. hope what I want to do is clear to you thanks, Michael ----- Original Message ----- From: Igor Mohorigor.mohor at g...> To: Date: Mon May 7 10:23:45 CEST 2007 Subject: [oc] Question on Ethernet MAC 10/100 Mbps I also wander what confusion is in the Ethernet MAC. If you want to transfer data between the host CPU and PHY, you should use the MIIM interface. It is well described in the 802.3 specification and each PHY specification. All those that used Ethernet MAC IP Core, used it to configure the PHY and it is working fine. Regards, Igor Mohor On 5/3/07, attachment.html

Question on Ethernet MAC 10/100 Mbps by Unknown on May 10, 2007			Not available!
what I want to do is to send data across mac core to an external memory and I thought host interface could be external memory thus I want to send data from phy to HI(external memory). and I don't know what i need to configure so that the ethernet mac core will do that hope you get what I am trying to do thanks, Michael ----- Original Message ----- From: Guy Hutchison<<A HREF="http://www.opencores.org/mailman/listinfo/cores">ghutchis at g...</A>> To: Date: Mon May 7 18:34:21 CEST 2007 Subject: [oc] Question on Ethernet MAC 10/100 Mbps [q] It's possible that I'm confused instead. In the designes I've worked on, MIIM = MII Management, which is the little 2-wire interface that the MAC uses to talk to the PHY. It's used to configure the PHY, it's not used to try and get the PHY to send specific data packets. However, the original poster may have meant that MIIM = MII Media, which would be the data interface between MAC and PHY. How I read the original post was that the poster wanted to push data in through the host CPU interface to get the MAC to send some special CPU-defined packet. I guess the other way to read it is that he wanted to send info through the host data interface, which of course would be the right way to do things. - Guy On 5/7/07, Igor Mohor <attachment.html [q]> -------------- next part -------------- An HTML attachment was [/q] scrubbed... URL: attachment.html [/q] what I want to do is to send data across mac core to an external memory and I thought host interface could be external memory thus I want to send data from phy to HI(external memory). and I don't know what i need to configure so that the ethernet mac core will do that hope you get what I am trying to do thanks, Michael ----- Original Message ----- From: Guy Hutchisonghutchis at g...> To: Date: Mon May 7 18:34:21 CEST 2007 Subject: [oc] Question on Ethernet MAC 10/100 Mbps It's possible that I'm confused instead. In the designes I've worked on, MIIM = MII Management, which is the little 2-wire interface that the MAC uses to talk to the PHY. It's used to configure the PHY, it's not used to try and get the PHY to send specific data packets. However, the original poster may have meant that MIIM = MII Media, which would be the data interface between MAC and PHY. How I read the original post was that the poster wanted to push data in through the host CPU interface to get the MAC to send some special CPU-defined packet. I guess the other way to read it is that he wanted to send info through the host data interface, which of course would be the right way to do things. - Guy On 5/7/07, Igor Mohor > -------------- next part -------------- An HTML attachment was scrubbed... URL: attachment.html

Question on Ethernet MAC 10/100 Mbps by Unknown on May 10, 2007			Not available!
If you take the wishbone spec (you'll find that somewhere on the Opencores website), you'll see how the interface is done. To understand how to operate with Ethernet MAC IP Core, you need to read the RX and TX Buffer Description in the Ethernet Specification. The general idea is to have some memory connected to the system (via memory interface that uses wishbone (this is not part if Eth MAC)). In case that you want to send the data, you need to store the packet to that memory and then you tell the Ethernet MAC where the packet is located by setting the proper BD (buffer descriptor). Once you set the "ready" bit in BD, Ethernet MAC takes the data from the address where the BD points to and sends it out. It is similar for reception. I'm not sure in which state the test bench is at this moment. I'm sure that most of things are working. I'm using a different test bench, which was improved a lot. I do that because I also provide the commercial license for the Ethernet MAC IP Core. It comes with all updates, improvements, higher throughput, support, etc. Regards, Igor On 5/10/07, <A HREF="http://www.opencores.org/mailman/listinfo/cores">yeuchaucheng at gmail.com</A> <<A HREF="http://www.opencores.org/mailman/listinfo/cores">yeuchaucheng at gmail.com</A>> wrote: [q] what I want to do is to send data across mac core to an external memory and I thought host interface could be external memory thus I want to send data from phy to HI(external memory). and I don't know what i need to configure so that the ethernet mac core will do that hope you get what I am trying to do thanks, Michael ----- Original Message ----- From: Guy Hutchison<<A HREF="http://www.opencores.org/mailman/listinfo/cores">ghutchis at g...</A>> To: Date: Mon May 7 18:34:21 CEST 2007 Subject: [oc] Question on Ethernet MAC 10/100 Mbps [q]> It's possible that I'm confused instead. In the designes I've > worked on, > MIIM = MII Management, which is the little 2-wire interface that > the MAC > uses to talk to the PHY. It's used to configure the PHY, it's not > used to > try and get the PHY to send specific data packets. > However, the original poster may have meant that MIIM = MII Media, > which > would be the data interface between MAC and PHY. > How I read the original post was that the poster wanted to push > data in > through the host CPU interface to get the MAC to send some special > CPU-defined packet. I guess the other way to read it is that he > wanted to > send info through the host data interface, which of course would be > the > right way to do things. > - Guy > On 5/7/07, Igor Mohor <attachment.html [q] > -------------- next part -------------- An HTML attachment was[/q] > scrubbed... URL: attachment.html >[/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] -------------- next part -------------- An HTML attachment was scrubbed... URL: <A HREF="http://www.opencores.org/forums.cgi/cores/attachments/20070510/b287d9e2/attachment.htm">http://www.opencores.org/forums.cgi/cores/attachments/20070510/b287d9e2/attachment.htm</A> If you take the wishbone spec (you'll find that somewhere on the Opencores website), you'll see how the interface is done. To understand how to operate with Ethernet MAC IP Core, you need to read the RX and TX Buffer Description in the Ethernet Specification. The general idea is to have some memory connected to the system (via memory interface that uses wishbone (this is not part if Eth MAC)). In case that you want to send the data, you need to store the packet to that memory and then you tell the Ethernet MAC where the packet is located by setting the proper BD (buffer descriptor). Once you set the "ready" bit in BD, Ethernet MAC takes the data from the address where the BD points to and sends it out. It is similar for reception. I'm not sure in which state the test bench is at this moment. I'm sure that most of things are working. I'm using a different test bench, which was improved a lot. I do that because I also provide the commercial license for the Ethernet MAC IP Core. It comes with all updates, improvements, higher throughput, support, etc. Regards, Igor On 5/10/07, yeuchaucheng at gmail.com yeuchaucheng at gmail.com> wrote: what I want to do is to send data across mac core to an external memory and I thought host interface could be external memory thus I want to send data from phy to HI(external memory). and I don't know what i need to configure so that the ethernet mac core will do that hope you get what I am trying to do thanks, Michael ----- Original Message ----- From: Guy Hutchisonghutchis at g...> To: Date: Mon May 7 18:34:21 CEST 2007 Subject: [oc] Question on Ethernet MAC 10/100 Mbps > It's possible that I'm confused instead. In the designes I've > worked on, > MIIM = MII Management, which is the little 2-wire interface that > the MAC > uses to talk to the PHY. It's used to configure the PHY, it's not > used to > try and get the PHY to send specific data packets. > However, the original poster may have meant that MIIM = MII Media, > which > would be the data interface between MAC and PHY. > How I read the original post was that the poster wanted to push > data in > through the host CPU interface to get the MAC to send some special > CPU-defined packet. I guess the other way to read it is that he > wanted to > send info through the host data interface, which of course would be > the > right way to do things. > - Guy > On 5/7/07, Igor Mohor > -------------- next part -------------- An HTML attachment was > scrubbed... URL: attachment.html > _______________________________________________ http://www.opencores.org/mailman/listinfo/cores -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20070510/b287d9e2/attachment.htm

Question on Ethernet MAC 10/100 Mbps by Unknown on May 11, 2007			Not available!
You can do it even simpler. Put a switch to each MII signal and control them manually using your hands :) Regards, Igor On 5/11/07, <A HREF="http://www.opencores.org/mailman/listinfo/cores">des00 at opencores.org</A> <<A HREF="http://www.opencores.org/mailman/listinfo/cores">des00 at opencores.org</A>> wrote: [q] Hi all! There is more simple variant, the truth it demands more time and require reverse engeneering experience. It is possible to cut out from IP all units concerning to a host interface and will leave only the transmitter and the receiver management signals . In total such signals is 12: TxClk, TxUsedData : in std_ulogic; TxData : out std_logic_vector (7 downto 0); TxStartFrm, TxEndFrm : out std_ulogic ; TxUnderRun : out std_ulogic ; -- eth_top Rx interface RxClk : in std_ulogic ; RxData : in std_logic_vector ( 7 downto 0); RxValid : in std_ulogic ; RxStartFrm, RxEndFrm : in std_ulogic ; TxPauseReq : out std_ulogic After that it is possible to connect to these signals anything you like. For example 2 FIFO and FSM which will operate transfer and reception. Thanks Igor Mohor, his verilog code is reading clearly enough and simply. _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] -------------- next part -------------- An HTML attachment was scrubbed... URL: <A HREF="http://www.opencores.org/forums.cgi/cores/attachments/20070511/a7e4a7a1/attachment.htm">http://www.opencores.org/forums.cgi/cores/attachments/20070511/a7e4a7a1/attachment.htm</A> You can do it even simpler. Put a switch to each MII signal and control them manually using your hands :) Regards, Igor On 5/11/07, des00 at opencores.org des00 at opencores.org> wrote: Hi all! There is more simple variant, the truth it demands more time and require reverse engeneering experience. It is possible to cut out from IP all units concerning to a host interface and will leave only the transmitter and the receiver management signals . In total such signals is 12: TxClk, TxUsedData : in std_ulogic; TxData : out std_logic_vector (7 downto 0); TxStartFrm, TxEndFrm : out std_ulogic ; TxUnderRun : out std_ulogic ; -- eth_top Rx interface RxClk : in std_ulogic ; RxData : in std_logic_vector ( 7 downto 0); RxValid : in std_ulogic ; RxStartFrm, RxEndFrm : in std_ulogic ; TxPauseReq : out std_ulogic After that it is possible to connect to these signals anything you like. For example 2 FIFO and FSM which will operate transfer and reception. Thanks Igor Mohor, his verilog code is reading clearly enough and simply. _______________________________________________ http://www.opencores.org/mailman/listinfo/cores -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20070511/a7e4a7a1/attachment.htm

Question on Ethernet MAC 10/100 Mbps by des00 on May 11, 2007			des00 Posts: 3 Joined: Feb 4, 2008 Last seen: Jan 25, 2011
Hi all! There is more simple variant, the truth it demands more time and require reverse engeneering experience. It is possible to cut out from IP all units concerning to a host interface and will leave only the transmitter and the receiver management signals . In total such signals is 12: TxClk, TxUsedData : in std_ulogic; TxData : out std_logic_vector (7 downto 0); TxStartFrm, TxEndFrm : out std_ulogic ; TxUnderRun : out std_ulogic ; -- eth_top Rx interface RxClk : in std_ulogic ; RxData : in std_logic_vector ( 7 downto 0); RxValid : in std_ulogic ; RxStartFrm, RxEndFrm : in std_ulogic ; TxPauseReq : out std_ulogic After that it is possible to connect to these signals anything you like. For example 2 FIFO and FSM which will operate transfer and reception. Thanks Igor Mohor, his verilog code is reading clearly enough and simply. Hi all! There is more simple variant, the truth it demands more time and require reverse engeneering experience. It is possible to cut out from IP all units concerning to a host interface and will leave only the transmitter and the receiver management signals . In total such signals is 12: TxClk, TxUsedData : in std_ulogic; TxData : out std_logic_vector (7 downto 0); TxStartFrm, TxEndFrm : out std_ulogic ; TxUnderRun : out std_ulogic ; -- eth_top Rx interface RxClk : in std_ulogic ; RxData : in std_logic_vector ( 7 downto 0); RxValid : in std_ulogic ; RxStartFrm, RxEndFrm : in std_ulogic ; TxPauseReq : out std_ulogic After that it is possible to connect to these signals anything you like. For example 2 FIFO and FSM which will operate transfer and reception. Thanks Igor Mohor, his verilog code is reading clearly enough and simply.

Question on Ethernet MAC 10/100 Mbps by Unknown on May 13, 2007			Not available!
MIIM uses 2 signals MDC and MDIO and is used for management purposes. You can control the PHY with it (mode of operation, link status, etc) MII interface is used to transfer the data. And BDs are related to this operation. Regards, Igor On 5/14/07, <A HREF="http://www.opencores.org/mailman/listinfo/cores">yeuchau at gmail.com</A> <<A HREF="http://www.opencores.org/mailman/listinfo/cores">yeuchau at gmail.com</A>> wrote: [q] I thought MII Management does both, it can be used to write to PHY and ready from PHY. that's what it says in the spec, so I am assuming that I can read from phy and store in MIIM and use the BD to transmit the data from MIIM to the external memory(Host Interface). tell me if that is wrong thanks ----- Original Message ----- From: Guy Hutchison<<A HREF="http://www.opencores.org/mailman/listinfo/cores">ghutchis at g...</A>> To: Date: Mon May 7 18:34:21 CEST 2007 Subject: [oc] Question on Ethernet MAC 10/100 Mbps [q]> It's possible that I'm confused instead. In the designes I've > worked on, > MIIM = MII Management, which is the little 2-wire interface that > the MAC > uses to talk to the PHY. It's used to configure the PHY, it's not > used to > try and get the PHY to send specific data packets. > However, the original poster may have meant that MIIM = MII Media, > which > would be the data interface between MAC and PHY. > How I read the original post was that the poster wanted to push > data in > through the host CPU interface to get the MAC to send some special > CPU-defined packet. I guess the other way to read it is that he > wanted to > send info through the host data interface, which of course would be > the > right way to do things. > - Guy > On 5/7/07, Igor Mohor <attachment.html [q] > -------------- next part -------------- An HTML attachment was[/q] > scrubbed... URL: attachment.html >[/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] -------------- next part -------------- An HTML attachment was scrubbed... URL: <A HREF="http://www.opencores.org/forums.cgi/cores/attachments/20070514/161c92ad/attachment.htm">http://www.opencores.org/forums.cgi/cores/attachments/20070514/161c92ad/attachment.htm</A> MIIM uses 2 signals MDC and MDIO and is used for management purposes. You can control the PHY with it (mode of operation, link status, etc) MII interface is used to transfer the data. And BDs are related to this operation. Regards, Igor On 5/14/07, yeuchau at gmail.com yeuchau at gmail.com> wrote: I thought MII Management does both, it can be used to write to PHY and ready from PHY. that's what it says in the spec, so I am assuming that I can read from phy and store in MIIM and use the BD to transmit the data from MIIM to the external memory(Host Interface). tell me if that is wrong thanks ----- Original Message ----- From: Guy Hutchisonghutchis at g...> To: Date: Mon May 7 18:34:21 CEST 2007 Subject: [oc] Question on Ethernet MAC 10/100 Mbps > It's possible that I'm confused instead. In the designes I've > worked on, > MIIM = MII Management, which is the little 2-wire interface that > the MAC > uses to talk to the PHY. It's used to configure the PHY, it's not > used to > try and get the PHY to send specific data packets. > However, the original poster may have meant that MIIM = MII Media, > which > would be the data interface between MAC and PHY. > How I read the original post was that the poster wanted to push > data in > through the host CPU interface to get the MAC to send some special > CPU-defined packet. I guess the other way to read it is that he > wanted to > send info through the host data interface, which of course would be > the > right way to do things. > - Guy > On 5/7/07, Igor Mohor > -------------- next part -------------- An HTML attachment was > scrubbed... URL: attachment.html > _______________________________________________ http://www.opencores.org/mailman/listinfo/cores -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20070514/161c92ad/attachment.htm

Question on Ethernet MAC 10/100 Mbps by Unknown on May 14, 2007			Not available!
I thought MII Management does both, it can be used to write to PHY and ready from PHY. that's what it says in the spec, so I am assuming that I can read from phy and store in MIIM and use the BD to transmit the data from MIIM to the external memory(Host Interface). tell me if that is wrong thanks ----- Original Message ----- From: Guy Hutchison<<A HREF="http://www.opencores.org/mailman/listinfo/cores">ghutchis at g...</A>> To: Date: Mon May 7 18:34:21 CEST 2007 Subject: [oc] Question on Ethernet MAC 10/100 Mbps [q] It's possible that I'm confused instead. In the designes I've worked on, MIIM = MII Management, which is the little 2-wire interface that the MAC uses to talk to the PHY. It's used to configure the PHY, it's not used to try and get the PHY to send specific data packets. However, the original poster may have meant that MIIM = MII Media, which would be the data interface between MAC and PHY. How I read the original post was that the poster wanted to push data in through the host CPU interface to get the MAC to send some special CPU-defined packet. I guess the other way to read it is that he wanted to send info through the host data interface, which of course would be the right way to do things. - Guy On 5/7/07, Igor Mohor <attachment.html [q]> -------------- next part -------------- An HTML attachment was [/q] scrubbed... URL: attachment.html [/q] I thought MII Management does both, it can be used to write to PHY and ready from PHY. that's what it says in the spec, so I am assuming that I can read from phy and store in MIIM and use the BD to transmit the data from MIIM to the external memory(Host Interface). tell me if that is wrong thanks ----- Original Message ----- From: Guy Hutchisonghutchis at g...> To: Date: Mon May 7 18:34:21 CEST 2007 Subject: [oc] Question on Ethernet MAC 10/100 Mbps It's possible that I'm confused instead. In the designes I've worked on, MIIM = MII Management, which is the little 2-wire interface that the MAC uses to talk to the PHY. It's used to configure the PHY, it's not used to try and get the PHY to send specific data packets. However, the original poster may have meant that MIIM = MII Media, which would be the data interface between MAC and PHY. How I read the original post was that the poster wanted to push data in through the host CPU interface to get the MAC to send some special CPU-defined packet. I guess the other way to read it is that he wanted to send info through the host data interface, which of course would be the right way to do things. - Guy On 5/7/07, Igor Mohor > -------------- next part -------------- An HTML attachment was scrubbed... URL: attachment.html

Question on Ethernet MAC 10/100 Mbps by Unknown on May 16, 2007			Not available!
OK now I am focus on getting data out for PRSD register in the MIIM and pass it on to the external memory which will be connect thru Host Interface. so, what exactly do I need to set, is the Transmit Buffer Descriptor the only thing I need to set. if not what else is required in this transmission. thanks, Michael ----- Original Message ----- From: Igor Mohor<<A HREF="http://www.opencores.org/mailman/listinfo/cores">igor.mohor at g...</A>> To: Date: Sun May 13 23:29:08 CEST 2007 Subject: [oc] Question on Ethernet MAC 10/100 Mbps [q] MIIM uses 2 signals MDC and MDIO and is used for management purposes. You can control the PHY with it (mode of operation, link status, etc) MII interface is used to transfer the data. And BDs are related to this operation. Regards, Igor On 5/14/07, attachment-0001.html [/q] OK now I am focus on getting data out for PRSD register in the MIIM and pass it on to the external memory which will be connect thru Host Interface. so, what exactly do I need to set, is the Transmit Buffer Descriptor the only thing I need to set. if not what else is required in this transmission. thanks, Michael ----- Original Message ----- From: Igor Mohorigor.mohor at g...> To: Date: Sun May 13 23:29:08 CEST 2007 Subject: [oc] Question on Ethernet MAC 10/100 Mbps MIIM uses 2 signals MDC and MDIO and is used for management purposes. You can control the PHY with it (mode of operation, link status, etc) MII interface is used to transfer the data. And BDs are related to this operation. Regards, Igor On 5/14/07, attachment-0001.html

Question on Ethernet MAC 10/100 Mbps by des00 on May 24, 2007			des00 Posts: 3 Joined: Feb 4, 2008 Last seen: Jan 25, 2011
Hi everybody! Could you explain: how this MAC will be processed Pause frames in a mode r_PassAll = 0? In eth_maccontrol i found follow condition // Rx Done Interrupt always @ (posedge WB_CLK_I or posedge Reset) begin if(Reset) RxB_IRQ <=#Tp 1'b0; else if(RxStatusWrite & RxIRQEn & ReceivedPacketGood & (~ReceivedPauseFrm \| ReceivedPauseFrm & r_PassAll & (~r_RxFlow))) RxB_IRQ <=#Tp (~RxError); else RxB_IRQ <=#Tp 1'b0; end As I understand in a mode r_PassAll = 0 signal RxB_IRQ should not be exposed, but ReceivedPauseFrm is not Level signal in r_PassAll = 0 mode. Becouse in eth_recivercontorl there is // Pause Frame received always @ (posedge MRxClk or posedge RxReset) begin if(RxReset) ReceivedPauseFrm <=#Tp 1'b0; else if(RxStatusWriteLatched_sync2 & r_PassAll \| ReceivedPauseFrm & (~r_PassAll)) ReceivedPauseFrm <=#Tp 1'b0; else if(ByteCntEq16 & TypeLengthOK & OpCodeOK) ReceivedPauseFrm <=#Tp 1'b1; end ReceivedPauseFrm is 1 cycle pulse signal in mode r_PassAll = 0 and cannot be registred in assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision}; always @ (posedge MRxClk or posedge Reset) begin if(Reset) RxStatusInLatched <=#Tp 'h0; else if(LoadRxStatus) RxStatusInLatched <=#Tp RxStatusIn; end becouse LoadRxStatus is valid at the end of frame recive process. As i understant at reception of a PAUSE frame RxB_IRQ interrupt will be exposed! But that is not correct! Could somebody help me please ? :) Denis Hi everybody! Could you explain: how this MAC will be processed Pause frames in a mode r_PassAll = 0? In eth_maccontrol i found follow condition // Rx Done Interrupt always @ (posedge WB_CLK_I or posedge Reset) begin if(Reset) RxB_IRQ else if(RxStatusWrite & RxIRQEn & ReceivedPacketGood & (~ReceivedPauseFrm \| ReceivedPauseFrm & r_PassAll & (~r_RxFlow))) RxB_IRQ else RxB_IRQ end As I understand in a mode r_PassAll = 0 signal RxB_IRQ should not be exposed, but ReceivedPauseFrm is not Level signal in r_PassAll = 0 mode. Becouse in eth_recivercontorl there is // Pause Frame received always @ (posedge MRxClk or posedge RxReset) begin if(RxReset) ReceivedPauseFrm else if(RxStatusWriteLatched_sync2 & r_PassAll \| ReceivedPauseFrm & (~r_PassAll)) ReceivedPauseFrm else if(ByteCntEq16 & TypeLengthOK & OpCodeOK) ReceivedPauseFrm end ReceivedPauseFrm is 1 cycle pulse signal in mode r_PassAll = 0 and cannot be registred in assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision}; always @ (posedge MRxClk or posedge Reset) begin if(Reset) RxStatusInLatched else if(LoadRxStatus) RxStatusInLatched end becouse LoadRxStatus is valid at the end of frame recive process. As i understant at reception of a PAUSE frame RxB_IRQ interrupt will be exposed! But that is not correct! Could somebody help me please ? :) Denis

no use

no use

1/2

Next

Last

© copyright 1999-2026 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.