Hello all! For my project I have decided to take advantage of WishboneBuilder generator http://www.opencores.org/projects.cgi/web/wb_builder/overview but at modelling various systems i have encountered bugs of the generator which are not described in the documentation: 1. Generator cannot use tgd_o/tgd_i signals. 2. Generator donot generate Verilog HDL (generate only header of file with initial comments). 3. If to judge on VHDL code, in any case andor architecture is present. Whether such behaviour of the generator normal or it really bug? If it is a bug then why the bug report of IP is empty? For generation I use ActivePerl under WinXP system thanks, Denis Shekhalev