Any cores available which make extensive use of Verilog 2001? Especially the generate, for, if and case statements. Also multi-dimensional arrays.. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20070516/b33b428e/attachment.htm

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

David Buck wrote:

Although not Verilog evolution closely, i can see (from your post) that Verilog-2001 has just ripped-off some of the good stuff in VHDL. I'm not sure why would anyone want to right cores in a language (Verilog-2001, SystemVerilog) that most people are reluctant to learn (time investment) and use. 90% people would use either one: Verilog (1995), VHDL (1993). -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.0 (MingW32) Comment: Using GnuPG with Thunderbird - http://enigmail.mozdev.org iD8DBQFGSt3HMPiy0tCWlz4RAjgRAKCaSWfwNE+STVP+OuOZkNk5p3Z/5ACfSIA8 TQASdDqsM75Af6vYjjYUKZ0= =vij7 -----END PGP SIGNATURE-----

I haven't seen much relunctance to learn Verilog-2001. Most of it is pretty straightforwards, and makes writing your code easier. What I have seen is that tool vendors were very slow to add support for 2001 features, and did so piecemeal, with the result that designers are unwilling to use the new features because the benefit is slight (if you've been using Verilog a while, you figured out other ways to do the same thing), and it's unclear what tools later in the pipeline will break. I started using some of the basic 2001 statements 3-4 years ago, and although I used only the simplest statements (@* and inline port lists), I still ran into problems with tools in the flow that couldn't parse the netlist or gave incomplete support. Generate? Bah. That's what Perl/Python is for. - Guy On 5/16/07, Nikolaos Kavvadias nkavv at physics.auth.gr> wrote: -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20070516/e9cedb8a/attachment.htm