Hello! I'm trying to use the cf ffthttp://www.opencores.org/projects.cgi/web/cf_fft/overview>for a hardware speech recognition project i'm doing at university. I use quartus and an altera D2E board. I want to use the 1024 points, 8 bits FFT which compiles nicely ans fits nicely into the FPGA. The only problem is that I cannot get it to work at all in simulation. What I think I have figured out until now: - the data must be input in pairs - the 8 MSBs of the data inputs and outputs are the real part of the signal. the other bits are the imaginary part. - I must send a pulse one clock cycle before the data is ready to be read by the FFT module (I'm not really sure about this one) What I suppose: - the FFT module must be enables (ENABLE = 1) in order to work) - the FFT module should be reset (RESET = 1) before a FFT computation is performed. The problem I have is that when I perform a timing simulation of the FFT module nothing happens (the data outputs are all 0). I run the simulation for 2040 clock cycles so I assume thet even if the latency is very big, I should see at least a few results. In the simulation I input a 600 samples wide square pulse. Any help on how to make this thing work would be very appreciated. Thanks, Carlos -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20070610/213a7a75/attachment.htm