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how to integrate the cores?
by buenos on Jun 17, 2007
buenos
Posts: 15
Joined: Feb 5, 2008
Last seen: Feb 11, 2026
hi. i think i ask the most basic question what i can ask here, but i have to because i have not much ideas how to do that: how to integrate IP cores, given in verilog or VHDL files, to a Xilinx-ISE project? How to move existing timing constraints from exaple projects? what i investigated until now, is that i have to synthesize the cores with that ISE version, what the developers used. (otherwise its not possible to synthesize) then i have to move a netlist (NGC or Edif) to a new ise project. For example, I would like to use the PCI core which is written in ISE 5.2. if i synthesyze with something else than Ise 5.2 then there are lots of errors. I want to use Spartan-3-400 which is not supported by Ise 5.2, so i have to play with a netlists anyway. I found an appnote where they mention scripts, and command line xilinx tools. i am not a so advanced user to be able to use them. I can use the Windows GUI of the ISE, so I would like to work with it. 90% of my time, i work on board level design, so Windows based work on this, is enough for me. What i made until now (in HDL), are CPLD bus bridges simple peripherals and glue logic, and a simple VGA on SP3. So, -how to synthesize it? with example-application ucf file? (I synthesized with ISE5.2, when I made a new project and added the files) -how to put the resulting netlist into my VHDL project? (the project is the PCI core, and my own developed logic, and peripherals in VHDL) with a wrapper? how to make it, or get it? -if the core has timing constraints in the included exaple projects, how will them go into my final system? -is it possible to get the cores in edif or NGC netlists, already synthesized? (with some most common settings) -it would be good a tutorial about integrating these IPs. -This problem is true not for only the PCI core, but for any cores on the site. (for advanced users, its not a problem, but i am not so advanced in FPGA design flow. i think there are other people too) -how to get the whisbone interconnect modules? best regards, Istvan Nagy buenos at freemail.hu
no use no use 1/1 no use no use
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