Hello,

I have successfully used the ddr-sdr opencore to test discrete DDR chips
(HYB25D256), but would like to use this core with a Registered DIMM. As
far as I can see, the effective CL changes from 2 clocks to 3 clocks due
to the 1 clock delay that the register adds. Is there anything else I need
to keep in mind when trying to get the DIMM running with this core?

Other things that stand out:

1) S0# and S1# - Selects physical banks, currently S1# is disabled and S0# is
tied to cs (cs_qn) of the controller
2) CKE0 and CKE1 - CKE1 disabled and CKE0 tied to cke_q of the controller.

Hmm... what am I missing? (It must be something because DDR reads from any
address always return the last value that I wrote to DDR...).

Thanks for any input

- Stephan

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