Hi, I'm trying to synthesize the T51 core (T8052) with Xilinx ISE on a Spartan 3-1000. The problem is that the synthesis takes (literally) hours. I had to stop it after two hours, didn't even get to the place & route stage. Is this normal? What I noticed is that the IRAMs are synthesized as Distributed RAM, not Block RAM, probably because the read address is not registered. Is that the reason for the long run time? Some more information in this (german) forum post: http://www.mikrocontroller.net/topic/72114#new Thanks in advance, Andreas

Hi Andreas, Doesn't sound normal. I used to run synthesis of the TV80 core (similar size) + DUT into a Virtex-4 device, and synthesis was on the order of 5 minutes. Going from a new netlist to a BIT file took less than an hour. It will probably use distributed RAM because register files and various other parts are async read. The TV80 uses relatively small amounts of it, but the T51 may have significantly more. The only non-standard thing I did was to run the whole process from the command line. - Guy On 6/25/07, x-opencores.org at andreas-s.net x-opencores.org at andreas-s.net> wrote: -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20070625/70a45757/attachment.htm

Hi Andreas, this usually happens if the read port is described as asynchronous read, thus not triggered on a clock event. On http://www.mikrocontroller.net/topic/72114#new the second and third RAM cores do not have a clock connected to Port B. This will the issue.... Hope that helps. Greetings, Jörn On Jun 25, 2007, at 7:20 AM, x-opencores.org at andreas-s.net wrote:

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 x-opencores.org at andreas-s.net wrote: I don't have any experience with the T51 core, but I also suffered from extreme synthesis times on the wb_z80 core. When I came back to it later, and replaced the RAM with an explicit Xilinx BRAM instantiation, everything was much quicker. I guess re-writing the RAM inference code to register the output might have had the same effect, but I didn't try that. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.2 (MingW32) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFGgJbchk3bo0lNTrURAma0AJsHIQny7tP0JJAiQJhH8nGkqzAagwCcDCc+ 4SNi/7Qkt0lwXS1gdXKUVGE= =QKnW -----END PGP SIGNATURE-----

Thanks for all the replies. The reason was the ROM. ISE didn't manage to infer a block RAM from the select-case-structure. I changed it to a array, now everything is OK. Andreas ----- Original Message ----- From: Guy Hutchisonghutchis at g...> To: Date: Mon Jun 25 20:35:29 CEST 2007 Subject: [oc] Problem with T51 core & Xilinx ISE