Hello,

We are trying to use the i2c_master_byte_ctrl.vhd (and the bit
controller of course) without the wishbone Interface and trying to
develop a test state machine like in the "State machine for reading
data from Dallas 1621" sample.

We are using the following ports of the MAsterbyte Controller
[code]
clk => clk, -- Byte => bit
ena => ena,
rst => rst,
scl_i => scl_i,
sda_i => sda_i,
clk_cnt => clk_cnt,
nReset => nReset,
read => read,
write => write,
start => start,
stop => stop,

ack_in => ack,
cmd_ack => cmd_ack,
din => D,
dout => Dout,
ack_out => lack,
scl_oen => SCL,
sda_oen => SDA
[/code]

But when starting the whole process, the SDA line signales a start ,
then the address + r/w is correctly added together by the
byte_controller, but the transmission is stopped through a stop
signal. This procedure repeats infinite times ..
Does someone have an idea why this occures ?


thanks

The fact that you're seeing activity shows you're on the right way. The byte controller uses a priority scheme; If start => generate start Elsif write => write byte Elsif read => read byte Elsif stop => generate stop Check your stop signal. I think it's asserted. Make sure you keep the control signals asserted until you get a cmd_ack from the byte controller; it's a hand-shaked state machine. Have fun!! Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of g-sus at gmx.li Sent: Tuesday, June 26, 2007 7:17 PM To: cores at opencores.org Subject: [oc] I2C clock timing / Masterbyte Controller / VHDL Hello, We are trying to use the i2c_master_byte_ctrl.vhd (and the bit controller of course) without the wishbone Interface and trying to develop a test state machine like in the "State machine for reading data from Dallas 1621" sample. We are using the following ports of the MAsterbyte Controller [code] clk => clk, -- Byte => bit ena => ena, rst => rst, scl_i => scl_i, sda_i => sda_i, clk_cnt => clk_cnt, nReset => nReset, read => read, write => write, start => start, stop => stop, ack_in => ack, cmd_ack => cmd_ack, din => D, dout => Dout, ack_out => lack, scl_oen => SCL, sda_oen => SDA [/code] But when starting the whole process, the SDA line signales a start , then the address + r/w is correctly added together by the byte_controller, but the transmission is stopped through a stop signal. This procedure repeats infinite times .. Does someone have an idea why this occures ? thanks _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

so we can't use a code like this to check for the next state ?
( similar to the DS1621 Sample Code)

[code]
when i2 => -- send "access config"
command
if (cmd_ack = '1') then
nxt_state := i3;
-- check aknowledge bit
if (lack = '1') then
ierr := '1'; -- no
acknowledge received from last command, expected ACK

end if;

istart := '0';
iread := '0';
iwrite := '1';
iack := '0';
istop := '0';
iD := x"AC";
end if;
[/code]

We noticed that the cmd_ack bit ( mapped to the cmd_ack bit of the
byte controller) never gets 1 (but it schould get set through the bit
controller). Is this a timingproblem, or is this approach completly
wrong ?

i2c_cmd_ack does get set to '1'; otherwise the code wouldn't work :p The i2c_master_controller uses a somewhat different approach then the simple_i2 controller. Run the i2c_master_controller's testbench to see the relationship between the signals. Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of g-sus at gmx.li Sent: Thursday, June 28, 2007 5:57 PM To: cores at opencores.org Subject: Re: [oc] I2C clock timing / Masterbyte Controller / VHDL so we can't use a code like this to check for the next state ? ( similar to the DS1621 Sample Code) [code] when i2 => -- send "access config" command if (cmd_ack = '1') then nxt_state := i3; -- check aknowledge bit if (lack = '1') then ierr := '1'; -- no acknowledge received from last command, expected ACK end if; istart := '0'; iread := '0'; iwrite := '1'; iack := '0'; istop := '0'; iD := x"AC"; end if; [/code] We noticed that the cmd_ack bit ( mapped to the cmd_ack bit of the byte controller) never gets 1 (but it schould get set through the bit controller). Is this a timingproblem, or is this approach completly wrong ? _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

A few comments; 1. SCL and SDA should be pulled to 'H', not set to '1'. I2C uses open-drain outputs. 2. I don't see SCL and SDA toggle in your timing diagram. Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of g-sus at gmx.li Sent: Wednesday, July 04, 2007 6:09 PM To: cores at opencores.org Subject: Re: [oc] I2C clock timing / Masterbyte Controller / VHDL hello again, while debugging all the core signals it was noticed that the al (arbitration lost bit) gets set in the bit controller. This seems to happen because of a delay while sending back the SCL und SDA line to the core at the highest level of our controller like this, [code] SCL http://www.imagehoster.info/images/Bild8-846b83.png (we are using the Quartus2 classic timing analyzer) i am very new to the VHDL Development and in urgent need off help with this problem ... thanks a lot PS : Is there some tutorial using I2C together with quartus ? ----- Original Message ----- From: Richard Herveillerichard at h...> To: Date: Sun Jul 1 07:00:46 CEST 2007 Subject: [oc] I2C clock timing / Masterbyte Controller / VHDL _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

hello again, while debugging all the core signals it was noticed that the al (arbitration lost bit) gets set in the bit controller. This seems to happen because of a delay while sending back the SCL und SDA line to the core at the highest level of our controller like this, [code] SCL http://www.imagehoster.info/images/Bild8-846b83.png (we are using the Quartus2 classic timing analyzer) i am very new to the VHDL Development and in urgent need off help with this problem ... thanks a lot PS : Is there some tutorial using I2C together with quartus ? ----- Original Message ----- From: Richard Herveillerichard at h...> To: Date: Sun Jul 1 07:00:46 CEST 2007 Subject: [oc] I2C clock timing / Masterbyte Controller / VHDL

Hi, Iam trying to use the simple i2c core (VHDL) in my project. Since my project involves a single master and a single slave , i thought simple i2c would be enough for my requirement rather than i2c_master_controller which is bit complex. iam using Cyclone II FPGA and Quartus II . i) whether the ip works only for Wishbone interface or can use the simple i2c core for any other interface? ii) ive replaced the DS1621 in the tst_1621 with AT24C02 and modified the code accordingly iemodified the code to write into AT24C02 and read back from the same location iii) Am having the AlteraDE2 board with Cyclone II and connected with AT24C02. Configured the FPGA with simpe12c and tst_1621(modified for 24C02). Nothing happens. i ve checked the hardware , clock and everything is ok iv)am not sure whether it is the problem if cmd_ack not getting set? kindly advice me on this ----- Original Message ----- From: Richard Herveillerichard at h...> To: Date: Wed Jul 4 15:46:38 CEST 2007 Subject: [oc] I2C clock timing / Masterbyte Controller / VHDL