Hello.

I have a question concerning WISHBONE signals.
I'm new to FPGA design, so maybe my question will seem to you rather
silly.

In WISHBONE specs, there is a place about BLOCK READ:

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CLOCK EDGE 0: MASTER presents a valid address on [ADR_O()] and [TGA_O()].
MASTER negates [WE_O] to indicate a READ cycle.
MASTER presents bank select [SEL_O()] to indicate where it expects
data.
MASTER asserts [CYC_O] and [TGC_O()] to indicate the start of the
cycle.
MASTER asserts [STB_O] to indicate the start of the first phase.

Note: the MASTER asserts [CYC_O] and/or [TGC_O()] at, or anytime
before, clock edge 1.

SETUP, EDGE 1: SLAVE decodes inputs, and responding SLAVE asserts
[ACK_I].
SLAVE presents valid data on [DAT_I()] and [TGD_I()].
MASTER monitors [ACK_I], and prepares to latch [DAT_I()] and
[TGD_I()].

CLOCK EDGE 1: MASTER latches data on [DAT_I()] and [TGD_I()].
MASTER presents new [ADR_O()] and [TGA_O()].
MASTER presents new bank select [SEL_O()] to indicate where it
expects data.
-------------------------------------------------------------

So, at the rising edge 1 master sees ACK from slave and latches data.
But before the same edge, master should present new address on ADR_O!
But how master knows in advance, that slave will assert ACK on edge 1?
Here I assume that all input signals are sampled on the rising edge of
clock. And since all input signals are synchronously latched on rising
edge, master really don't have any chance to peek into slave signals
before the rising edge.

darus at mail.ru wrote: Umm, no, the new address is asserted in logic clocked on clock edge 1, so it will appear _after_ that clock edge - as in figure 3-6! The master is only going to present a new address if it samples ACK_I on that clock edge. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266