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Translation
by Unknown on Feb 4, 2004 |
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>
> Right! > But I want to make a process with various waits referencin g to multiple
> signals/ports! At level of simulation this works! But I wa
nt to synthesize
> this code! And the program that I uses (Altera Quartus II)
doesn't
> accept/support more that one wait in a process! How can I
solve this?
>
Think about what you are asking and what is available in des ign cells.
You are asking for a circuit that triggers on multiple signa
ls, like a
flip-flop with multiple clock inputs?
Simulation/Modulation is much more flexible in what is allow ed and possible,
as the simulator just needs to execute the sequential code.
However translating this into hardware requires other techni ques and a more
restrict coding style. Stick to the convention and it will w
ork, do
something weird and you're on your own.
If you wrote a piece of code (converted or not) that is not synthesizable
and that was intended to be synthesizable, then you did a ba
d job. This is
not the synthesizer's fault, so don't blame it on Quartus.
Go back to the original code and rewrite it so it is synthes izable, or pay
somebody to do it for you.
Richard
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
OK!
I will give you the structure of the code that I want to
translate and then you see if you can help me!
//process.h
#include
SC_MODULE(name)
{
sc_in > portA;
sc_in > portB;
sc_in > portC;
sc_out > portD;
sc_out > portE;
sc_out > portF;
sc_in signalA;
sc_in signalB;
sc_in signalC;
sc_in reset;
sc_in_clk clock;
void process();
SC_CTOR(name)
{
SC_CTHREAD(process,clock.pos());
watching(reset == true);
}
}
//process.cpp
#include "process.h"
name::process()
{
...
wait_until(portA == true);
...
wait_until(portB == true);
...
wait_until(portC == true);
...
}
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