How can I implement an SC_CTHREAD process in VHDL?

Hi,

Here you find an extract out of the manual of Behavioral compiler from
Synopsys which shows you basically that SC_CTHREAD has been added to systemC
in order to be able to "reuse" behavioral compiler with systemC.



entity comp_mult is
port(
reset : in bit;
clk : in bit;
in_data : in integer range -128 to 127;
in_data_ready : in bit;
out_ready_for_data : out bit;
out_real : out integer range -32768 to 32767;
out_imag : out integer range -32768 to 32767);
end comp_mult;

architecture behav of comp_mult is
begin
main_process : process
begin
reset_loop : loop
out_ready_for_data out_real out_imag wait until clk'event and clk = '1';
if (reset = '1') then exit reset_loop;
end if;
main_loop : loop
handshake_loop : while (in_data_ready = '0') loop
wait until clk'event and clk = '1';
if (reset = '1') then exit reset_loop;
end if;
end loop handshake_loop;
wait until clk'event and clk = '1';
if (reset = '1') then exit reset_loop;
end if;
out_ready_for_data wait until clk'event and clk = '1';
if (reset = '1') then exit reset_loop;
end if;
out_ready_for_data wait until clk'event and clk = '1';
if (reset = '1') then exit reset_loop;
end if;
end loop main_loop;
end loop reset_loop
end process main_process;
end behav;

Redant Steven wrote:
-- Geert Vanwijnsberghe Project Engineer ASIC Design e-mail: vwb at imec.be IMEC, division INVOMEC phone : +32 16 281 273 Kapeldreef 75 fax : +32 16 281 584 B-3001 Leuven, Belgium ------------------------------------------------------------------------- This e-mail and/or its attachments may contain confidential information. It is intended solely for the intended addressee(s). Any use of the information contained herein by other persons is prohibited. IMEC vzw does not accept any liability for the contents of this e-mail and/or its attachments. -------------------------------------------------------------------------

piler from

added to systemC

emC.

-------------

mail and/or its attachments may contain confidential informati
on.

(s). Any use of the

IMEC vzw

mail and/or its

-------------
I think that you don't understand my question! Or I your answer! How can I translate a SC_CTHREAD process to VHDL? --- Acabe com aquelas janelinhas que pulam na sua tela. AntiPop-up UOL - É grátis! http://antipopup.uol.com.br

piler from

added to systemC

emC.

-------------

mail and/or its attachments may contain confidential informati
on.

(s). Any use of the

IMEC vzw

mail and/or its

-------------
My problem is that: My SC_CTHREAD have wait_until's of various signals/ports! It couldn't put wait_until's of different signals/ports in a VHDL process! --- Acabe com aquelas janelinhas que pulam na sua tela. AntiPop-up UOL - É grátis! http://antipopup.uol.com.br

You can do that. But you can't mix it with a sensitivity list. In SystemC you have the different wait's AND a sensitivity list. In VHDL it is either a sensitivity list OR waits in the process.
E.g. the code below.

process
begin

...
Wait on a;

...

wait on b;

...

wait on a;

end;

At 06:02 29/01/2004, you wrote:

You can do that. But you can't mix it with a sensitivity list. In SystemC you have the different wait's AND a sensitivity list. In VHDL it is either a sensitivity list OR waits in the process. E.g. the code below. process begin ... Wait on a; ... wait on b; ... wait on a; end; _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

You mean in VHDL? No that is not true from a strict VHDL language/simulator standpoint. For Behavioral compiler it is the case that you should have all the waits waiting for the same kind of clock-edge.

Steven

guage/simulator standpoint. For Behavioral compiler it is the
case that you should have all the waits waiting for the same k
ind of clock-edge.
Yes, at level of simulation this works. But the problem is that I want to synthetize this. The program that I use to this don't accept/support more than one wait in a process! How can I solve this problem? --- Acabe com aquelas janelinhas que pulam na sua tela. AntiPop-up UOL - É grátis! http://antipopup.uol.com.br

You do not use 'wait' to generate synchronous actions in VHDL.
If your translator generates this code, you'll have to rewrite it so it
uses:

clk'event and clk='1'
or
rising_edge(clk)

The above is good coding practice (for synthesis)
Using wait isn't. Although some synthesis tools allow you to use a single
'wait' in a process to generate synchronous designs.

Richard

Or use behavioral compiler with code that looks like Geert's example sent in a previous mail (i.e. several wait until rising_edge(clk) statements in one process).

Steven

At 07:21 30/01/2004, you wrote:

Or use behavioral compiler with code that looks like Geert's example sent in a previous mail (i.e. several wait until rising_edge(clk) statements in one process). Steven _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

The only way to make a process that waits on different signals is writing a combinatorial function using all these in the sensitivity list.

For synthesis you HAVE to stick to the rules. Synthesis on higher levels (i.e. choosing architecture from a higher level description) is possible for some specific kinds of architectures in (not free) EDA software, but there is still a gap here.

But I want to make a process with various waits referencing to multiple signals/ports! At level of simulation this works! But I want to synthesize this code! And the program that I uses (Altera Quartus II) doesn't accept/support more that one wait in a process! How can I solve this? _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

always@(posedge i_clk or negedge i_reset_n)begin if(!i_reset_n)begin //reset logic here end else begin if(sig_x==1'b1)begin //do something here end end end If you wanted to wait for the posedge of the clock and only execute when sig_x is high, this would work. If you are doing something like a FIFO where there are two clocks, you need to use seperate always blocks that are clocked to different clocks. One to write to your buffer and one to read from it. Also, if just want to cross a clock boundry, do the same thing but instead of using some memory, just double buffer the signal. We might be able to help you more if you tell us specifically what type of module you are trying to make. -Brian -----Original Message----- From: cores-bounces at opencores.org on behalf of Redant Steven Sent: Fri 1/30/2004 7:10 AM To: Discussion list about free open source IP cores Cc: Subject: RE: FW: [oc] Translation The only way to make a process that waits on different signals is writing a combinatorial function using all these in the sensitivity list. For synthesis you HAVE to stick to the rules. Synthesis on higher levels (i.e. choosing architecture from a higher level description) is possible for some specific kinds of architectures in (not free) EDA software, but there is still a gap here. But I want to make a process with various waits referencing to multiple signals/ports! At level of simulation this works! But I want to synthesize this code! And the program that I uses (Altera Quartus II) doesn't accept/support more that one wait in a process! How can I solve this? _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

At 14:22 30/01/2004, you wrote:

trigger on one edge of the clock and one edge of the reset. Any other
decisions should be done with if then statments.

Verilog, and this is what my code would look like: always@(posedge i_clk or negedge i_reset_n)begin if(!i_reset_n)begin //reset logic here end else begin if(sig_x==1'b1)begin //do something here end end end If you wanted to wait for the posedge of the clock and only execute when sig_x is high, this would work. If you are doing something like a FIFO where there are two clocks, you need to use seperate always blocks that are clocked to different clocks. One to write to your buffer and one to read from it. Also, if just want to cross a clock boundry, do the same thing but instead of using some memory, just double buffer the signal. We might be able to help you more if you tell us specifically what type of module you are trying to make. -Brian -----Original Message----- From: cores-bounces at opencores.org on behalf of Redant Steven Sent: Fri 1/30/2004 7:10 AM To: Discussion list about free open source IP cores Cc: Subject: RE: FW: [oc] Translation The only way to make a process that waits on different signals is writing a combinatorial function using all these in the sensitivity list. For synthesis you HAVE to stick to the rules. Synthesis on higher levels (i.e. choosing architecture from a higher level description) is possible for some specific kinds of architectures in (not free) EDA software, but there is still a gap here. > But I want to make a process with various waits referencing > to multiple > signals/ports! At level of simulation this works! But I want > to synthesize > this code! And the program that I uses (Altera Quartus II) doesn't > accept/support more that one wait in a process! How can I solve this? > > _______________________________________________ > http://www.opencores.org/mailman/listinfo/cores >

Think about what you are asking and what is available in design cells.
You are asking for a circuit that triggers on multiple signals, like a
flip-flop with multiple clock inputs?

Simulation/Modulation is much more flexible in what is allowed and possible,
as the simulator just needs to execute the sequential code.
However translating this into hardware requires other techniques and a more
restrict coding style. Stick to the convention and it will work, do
something weird and you're on your own.
If you wrote a piece of code (converted or not) that is not synthesizable
and that was intended to be synthesizable, then you did a bad job. This is
not the synthesizer's fault, so don't blame it on Quartus.

Go back to the original code and rewrite it so it is synthesizable, or pay
somebody to do it for you.

Richard