Hi, If I use keil 51 vision 8 to simulate, which target device(8052) is more compatible with t51 source code? The compile and simuation result is independent on target device ,isn't it? (Different 8052 target device has different instruction cycle) Who can help me? Thanks in advance! wwang _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

IMHO: Keil 8: Strength • Ideal for rapid code development • Cycle-accurate Instruction Set Simulation (ISS) • Single-step • Breakpoints • Intimate interaction with 8052 registers, flags, and memory values • Code coverage indicator • Software timing • Basic system-level simulation via file I/O functions Weakness •No modeling of custom logic attached to the 8052 microcontroller ////////////////////////////////////////////////////////////////////////// ModelSim Strength • Holistic simulation of 8052 microcontroller with associated FPGA logic • VHDL and Verilog logic and timing simulation • Cycle and timing accurate with FPGA hardware Weakness • Requires simulator setup and stimulus files • Digital simulator, not an ideal Instruction Set Simulation environment ////////////////////////////////////////////////////////////////////////// In-system on FPGA Strength • Fast, real-time performance • Ideal for complex interactions • Integrated with peripherals, displays, UARTs, etc. Weakness • Poor visibility of register contents On 7/27/07, wei.wang at polarismicro.com wei.wang at polarismicro.com> wrote:

IMHO: Keil 8: Strength • Ideal for rapid code development • Cycle-accurate Instruction Set Simulation (ISS) • Single-step • Breakpoints • Intimate interaction with 8052 registers, flags, and memory values • Code coverage indicator • Software timing • Basic system-level simulation via file I/O functions Weakness •No modeling of custom logic attached to the 8052 microcontroller ////////////////////////////////////////////////////////////////////////// ModelSim Strength • Holistic simulation of 8052 microcontroller with associated FPGA logic • VHDL and Verilog logic and timing simulation • Cycle and timing accurate with FPGA hardware Weakness • Requires simulator setup and stimulus files • Digital simulator, not an ideal Instruction Set Simulation environment ////////////////////////////////////////////////////////////////////////// In-system on FPGA Strength • Fast, real-time performance • Ideal for complex interactions • Integrated with peripherals, displays, UARTs, etc. Weakness • Poor visibility of register contents On 7/27/07, wei.wang at polarismicro.com wrote:
device(8052) is more

result is

device has