Hello Cores,

I am sorry if my question isn't directly related to the theme of this
mailing list,
but maybe could someone please help me to understand,
what is the general difficulties in creating open source tools for
digital design/synthesis ?

I suppose it is the same problem like in the case of open source
drivers (e.g. ATI or NVIDIA), because HW Developers do not open their
specifications. But, on the other side, using proprietary FPGA-design
tools you can inspect FPGA ICs interior very precisely.

It is really hard to tolerate all this poor designed, slow proprietary
design/synthesis tools like Xilinx ISO. I wonder if we will have good
FPGA-design Linux tools ever, like todays perfect GCC compiler tools.

Thanks,
Vadim

On Sunday 29 July 2007 20:45:21 vkataev at mail.uni-paderborn.de wrote: It is inevitable. It's only a question of when. Cheers. -- with metta, Shawn Tan Aeste Works (M) Sdn Bhd - Engineering Elegance http://www.aeste.net

There is still a very long way to go. Someone recently managed to do an 8 bit adder though: http://research.cs.berkeley.edu/project/slipway/ Philipp

vkataev at mail.uni-paderborn.de wrote:

You should look in the archive of this list. There has been a lengthy
discussion about this topic a few years ago (2004). Even Richard
Stallman took part in it.

It will give you some insight about the problem.



I think the main problem is that there is not a big group of people
willing to tackle the problem. At the end when I look how people reverse
engineer WLAN chips to write the driver, take for example the bc4xx, the
task to figure out the FPGAs cannot be that much harder.

But look at opencores. There are not many projects with more than two
developers. And the people doing the projects want to spend the time to
use the tools to do their logic development and not develop the tools.

Also most of the people are Electrical Engineers and not Software
Engineers and it is hard to convince a Software Engineer to develop a
software as open source that s/he will probably never use him/her self.

A good example for this is Icarus Verilog the simulator/synthesis tool.
It is getting developed all these years by mainly one person.


Cheers,

Guenter

On Tuesday 31 July 2007 09:50:30 Günter Dannoritzer wrote:
I think that you've pretty much nailed it there. However, this applies to a grass root movement to produce an Open Source tool. There is another possibility, such as an existing tool vendor, opening up their source code. They could potentially use some form of dual-license for hobby/academic versus commercial use. They can also isolate the proprietary bits and open up only some parts of the software. This could happen for FPGA vendors as their main business is selling chips. Opening software up can increase community participation, reduce maintenance costs and generate good will, which may help them sell more chips. I see this happening eventually. However, I do not see this happening for the ASIC tool vendors, who make money on the secret sauces they put inside their software. I'd settle for industry wide standard file formats. This would allow designers to mix + match tool chains with design libraries and fab processes. Cheers. -- with metta, Shawn Tan Aeste Works (M) Sdn Bhd - Engineering Elegance http://www.aeste.net

On Tue, 31 Jul 2007 19:01:08 +0100 Shawn Tan shawn.tan at aeste.net> wrote:

Apropos standard file formats, i've been looking for documentation
on the EDIF standard(s)for quite some time now but couldn't find anything
usable. Yes, i could buy the standards, but 400CHF is kind of expensive
just to have a look and decide whether it's worth to invest time and
energy into doing some OSS tools around EDIF.

Does anyone know any good sources for EDIF?

Thanks in advance

Attila Kinali
--
Praised are the Fountains of Shelieth, the silver harp of the waters,
But blest in my name forever this stream that stanched my thirst!
-- Deed of Morred

The EDIF standard is available for download from IEEE for $9. I am sure there are IEEE members/fellows on this list that can assist in obtaining the standard as a contribution to open source tools. You can also take a look at the OADB. If I am not mistaken it has an EDIF reader, plus verilog, vhdl, and DEF readers. That would be a good starting point for an open source tool. Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of Attila Kinali Sent: Wednesday, August 01, 2007 10:02 AM To: Discussion list about free open source IP cores Subject: Re: [oc] future of open source fpga design tools On Tue, 31 Jul 2007 19:01:08 +0100 Shawn Tan shawn.tan at aeste.net> wrote:
money

industry


Apropos standard file formats, i've been looking for documentation on the EDIF standard(s)for quite some time now but couldn't find anything usable. Yes, i could buy the standards, but 400CHF is kind of expensive just to have a look and decide whether it's worth to invest time and energy into doing some OSS tools around EDIF. Does anyone know any good sources for EDIF? Thanks in advance Attila Kinali -- Praised are the Fountains of Shelieth, the silver harp of the waters, But blest in my name forever this stream that stanched my thirst! -- Deed of Morred _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

Shawn Tan wrote:


I think the Slipway demo board and any new project rumored by Mr. Magacz to be
"well under way" will help a lot by showing unique function is possible by fine
grained access to the P&R functions of FPGAs. I have one person interested in
a copy of a slipway board -- I'm amking a run of them -- anyone else?

John Griessen
Ecosensory
(Systems engineerand software user. EE mostly -- Software Engineer only slightly)

On Wed, 1 Aug 2007 15:53:18 +0200 "Richard Herveille" richard at herveille.net> wrote:

Interesting. Being myself an IEEE memeber i first looked there,
but couldn't find anything usefull, neither with google nor ieeexplore.
Could you point me to the webpage with the EDIF standard?



Yes, i had a look at it, but i don't like to look at an implementation
to understand how a standard works. So, for the beginning i'd rather
like to have a look at the standard itself before diving further
in to the available EDIF code base.

Attila Kinali

--
Praised are the Fountains of Shelieth, the silver harp of the waters,
But blest in my name forever this stream that stanched my thirst!
-- Deed of Morred

Yes, i had a look at it, but i don't like to look at an implementation
to understand how a standard works. So, for the beginning i'd rather
like to have a look at the standard itself before diving further
in to the available EDIF code base.