Hi Cores,
I've been using Opencores.org for a long time now but most of the time
had to change the cores to fit my requirements so I did not have a
chance of giving something back.
In my recent project I needed a standard viterbi decoder like the one
used by the IEEE802. I found the VHCG project also published here and
generated the IP. After fixing some bugs and adding a feature to
support packet transmissions the core is now working in simulation and
was synthesised successfully for a Xilinx FPGA.
I will have results of lab tests in about a month.
My question is, should I post the core as a sperate project under
Opencores?
I tried emailing the author of the VHCG project but he did not answer me.
Please advise.
Thanks,
Moti

Hi motilito!
Could you email me your codes, please? I need them.

abolfazltorki@gmail.com

Thanks a lot