Sir, I am doing a project with spartan3 FPGA and is in a process interfacing the essential peripherals like AC 97,VGA etc with it. I intend to keep it opensource and hence i am using Wishbone. I would like to know how to simulate this core in ISE or Modelsim. The simulation requires either .tcl or .xco file. Please suggest a method to run these verilog codes. Thanks & Regards Aditya Pandit ----- Original Message ----- From: Rudolf Usselmann rudi at a...> To: OPENCORES cores at o...> Date: Sat, 05 May 2001 08:39:42 +0700 Subject: [oc] AC97 Controller