Hello all,

I would like to use the wishbone-ahb bridge to implement the connection
betweem wishbone bus and ARM bus.

However, I find that the core is single tranfer function only. the burst
tranfer function is no implement.

I would like to implement the burst transfer function. so, please give me
information about the burst transfer function.

Thanks

so

Basically AHB complies with increment, Burst, Wrap and size operations. Address will be incremented by 4 for any operation other than single operations. The Increment or burst operation could be implemented the way its implemented by single operations, Only thing is that you have to do with the instrumentation functionalities . -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of so Sent: Monday, August 13, 2007 10:36 AM To: cores at opencores.org Subject: [oc] the problem of wishbone-ahb bridge Hello all, I would like to use the wishbone-ahb bridge to implement the connection betweem wishbone bus and ARM bus. However, I find that the core is single tranfer function only. the burst tranfer function is no implement. I would like to implement the burst transfer function. so, please give me information about the burst transfer function. Thanks so _______________________________________________ http://www.opencores.org/mailman/listinfo/cores DISCLAIMER: This email (including any attachments) is intended for the sole use of the intended recipient/s and may contain material that is CONFIDENTIAL AND PRIVATE COMPANY INFORMATION. Any review or reliance by others or copying or distribution or forwarding of any or all of the contents in this message is STRICTLY PROHIBITED. If you are not the intended recipient, please contact the sender by email and delete all copies; your cooperation in this regard is appreciated.