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(EDK)access of common address range by multiple masters
by Unknown on Aug 20, 2007 |
Not available! | ||
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hi,
i am currently using xilinx EDK 8.2 working on a V2pro prototype board. i had a requirement which i dont know if possible or not. i am about to design a system which uses dual port memory. i am using SDRAMs for that. i have included a custom IP which is needed to write data into the SDRAMs and also i need to read/write data into SDRAMs from ppc405 core. is this possible? i am using OPB interface for SDRAM and custom IP. i have tried to use the custom ip with MSOPB interface but faced problem with addressing. can u help me out with this. if you require any more details please contact me through my email id srinivas |
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(EDK)access of common address range by multiple masters
by Unknown on Aug 27, 2007 |
Not available! | ||
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Hi there,
Myself kiran garje. I am also working on EDK 8.2. I am using
sparton 3E beginner kit. Facing lot sof problem while doing accessing the
peripheral of the kit. Need little help.
Kiran
----- Original Message -----
From: vasu_mudumba at yahoo.comvasu_mudumba at y...>
To:
Date: Mon Aug 20 22:00:40 CEST 2007
Subject: [oc] (EDK)access of common address range by multiple
masters
hi,
i am currently using xilinx EDK 8.2 working on a V2pro prototype board. i had a requirement which i dont know if possible or not. i am about to design a system which uses dual port memory. i am using SDRAMs for that. i have included a custom IP which is needed to write data into the SDRAMs and also i need to read/write data into SDRAMs from ppc405 core. is this possible? i am using OPB interface for SDRAM and custom IP. i have tried to use the custom ip with MSOPB interface but faced problem with addressing. can u help me out with this. if you require any more details please contact me through my email id srinivas |
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