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I am having trouble editing a signal in a sub program IN VHDL
by Unknown on Aug 29, 2007 |
Not available! | ||
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Change the assigment operator (cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] Em nome
de 14345609 at sun.ac.za
Enviada em: quarta-feira, 29 de agosto de 2007 16:19
Para: cores at opencores.org
Assunto: [oc] I am having trouble editing a signal in a sub program IN VHDL
I declared a signal called reg_A. I then want to edit the signal in another
subprogram. I basically want reg_A to be one of my inputs to a sub
program(ALU_test) edit reg_A in the subprogram and then I want the output of
my subprogram to change reg_A in the main program (test). When I tried to
do this an error occurred ("Signal reg_A has multiple sources"). I am not
sure what to do could some one please help me.
library ieee;
use ieee.std_logic_1164.all;
entity test is
port ( clk : in std_logic;
choze : in std_logic_vector(3 downto 0);
data_t : in std_logic_vector(7 downto 0);
Outw : out std_logic_vector(7 downto 0));
end entity test;
architecture no1 of test is
------------------------------------------------------------
component ALU_test is
port ( clk : in std_logic;
choose : in std_logic_vector(3 downto 0);
vlaggieIN : in std_logic_vector(7 downto 0);
vlaggie : out std_logic_vector(7 downto 0));
end component ALU_test;
------------------------------------------------------------
signal reg_A
: std_logic_vector(7 downto 0);
------------------------------------------------------------
begin
process (clk)
begin
if rising_edge(clk) then
reg_A
vlaggie
vlaggie
vlaggie
vlaggie http://www.opencores.org/mailman/listinfo/cores
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