I am trying to implement an i2c slave and asking myself if i need a
clock or can use the incoming SCL as clock. i am a real vhdl newbie
and build a slave that triggers on the rising edge of the SCL line for
reading the data ( except start and stop of course) and triggers on
the falling edge in order to set the statemachine (which determines
the next action) to the next state. Is this a correct and adequate way
for building an i2c slave ?

thnx for your help ..

Hi G-sus, I was faced with the same issue when I designed an i2c slave in the past. My decision was to use a higher speed clock to sample SCL and SDA. The rational was to allow digital debouncing of these signals since they have very slow transition times and are suceptible to noise induced glitches. If you do not think noise will be an issue in your environment you can the SCL as a clock. However, for detecting start and stop consitions, I recall that you need to use SDA as the clock and SCL as the data. Thanks ----- Original Message ----- From: g-sus at gmx.lig-sus at g...> To: Date: Sun Sep 2 15:52:10 CEST 2007 Subject: [oc] i2c Slave Design Ideas

tkafafi at hotmail.com Wrote:

Let me confirm this point. The I2C specification requires the rejection of up
to 50ns duration glitches. So use of a digital delay line that requires
multiple clocks worth of stability is a must to get I2C to work.

Don't forget that you can be driving up to 400pf worth of load - and the bus
is going to have significant reflections.

That digital filter seems to be a requirement in any significant (large)
applications - and least anything not point to point.

Steve Wilson

Hi all, I'm another newbie to I2C but learning fast (got the spec right here!) I'm currently looking at VHDL models for I2C slave designs (so far found the one by Frank Buss) but ultimately I want to implement an I2C slave in a custom CMOS mixed-signal IC. My first thoughts were, that it seems like FPGA designers have the luxury of "cheating" by using an external clock to register SDA and SCL. This makes it not a 2-wire interface, technically, but sure makes it easier. But since I cannot bring a high-speed clock onto my CMOS, I need to do it using only the two I2C bus clocks (I assume that commercial serial DAC makers do the same as they have no external clock pin). From what I've read in previous email posts related to this topic, it seems rational to try using both SDA and SCL as a clock (or latch), depending on the need. I would just like for someone who's already done this to confirm. My other guess is that chip makers generate their own clock from an internal multivibrator ckt or something. Does anyone have knowledge of a document, behavioral model, state diagram, logic diagram, etc, that would help me with designing an I2C slave (Fm or faster) that does not rely on an external clock? Thanks all. JP ----- Original Message ----- From: tkafafi at hotmail.comtkafafi at h...> To: Date: Tue Sep 25 09:04:10 CEST 2007 Subject: [oc] i2c Slave Design Ideas

Yes, it is possible to run an I2C interface without an external clock. The challenge is in detecting the start and stop transitions on the interface and using them to perform useful work. I do not have any un-encumbered code to share, but to summarize: Start transition: Use the falling edge of SDA to clock a flop with SCL as the D input. Use SCL low to reset the flop. The output of the flop is used to reset the interface state machine. State machine: Shift SDA into register on rising or falling edge of SCL. Falling edge is usually sharper, but you run into race conditions with the reset from the start transition. Stop transition: Use the rising edge of SDA to transfer the shift register into the working registers when SCL is high and the address matches. Please submit your design to opencores when complete. Regards, Clint On Sat, 29 Sep 2007, jpcmisc at charter.net wrote:

Hi Steve, I recall the i2c specification requires filtering for the fast and highspeed modes, but not necessarily for the standard mode (0 to 100KHz). But I agree with you that for any real world application you need the filtering. I was thinking more along the lines if this is a univeristy level project intended for operation in a lab environement, then you can drop the filtering requirement. Even in a commercial environement you may those to imlement the filtering in the analog domain. Such an approach may make sense if none of the pads in your library meet the drive requirements and you need to develop a custom pad for I2C, you may decide to through in the filtering in the pad too. ----- Original Message ----- From: Steve Wilsonstevew at k...> To: Date: Tue Sep 25 16:10:36 CEST 2007 Subject: [oc] i2c Slave Design Ideas

Hi Jpcmisc, Most of the ICs I have seen are SOCs with the I2C being one of the interfaces that is available. As such there is a system clock input to the chip which will go through an integrated PLL to generate the internal clocks needed by the SOC. The I2C functional block would simply use one of these internal clocks that is fast enough. Althought the internal clock is not part of the I2C interface, it is available for free. I would not consider this cheating, just a little sneaky. People usually do not generate clocks using miltivibrator circuits because there would be a significant uncertainty on the frequency because of the on-chip passive component value variation. But I guess in this case, where the clock is being used only for sampling an external interface, this uncertainty may be acceptable. Although majority of the designs I have seen utilise the above approach, I have heard about people (I think in phillips) using the SCL as a clock. The trick there is detecting and clearing start and stop conditions. If you look carefully, a start condition can be detected by using a D flip flop to sample SCL with the falling edge of SDA. A stop condition can be similarly detected by sampling SCL with the rising edge of SDA. You can clear these conditions asynchronously (using a pulse generator - an and gate with a buffer delay chain on one of the inputs or some other conditions depending on your statemachine). You probably want to add some delay to SDA in the above sampling flops to ensure you have enough setup/hold margin. Strictly speaking, the standard requires SDA to change only after the falling edge of SCL, but I've seen some controllers miss this point and transition both signals at the same time. Other than that, the statemachines should be fairly similar to those used in the first approach and are not very difficult to figure out. Hope this helps Thanks Tamer ----- Original Message ----- From: jpcmisc at charter.netjpcmisc at c...> To: Date: Sat Sep 29 06:12:30 CEST 2007 Subject: [oc] i2c Slave Design Ideas