1/1 
|
the errors of "tests.v" module?
by Unknown on Sep 13, 2007 |
Not available! | ||
|
hi,
At first,thanks for your AC'97 source code. when I do the compile by Modelsim there is some errors with the "tests.v" file, I.E. ** Error: E:/work/AC97/ac97_ctrl/bench/verilog/tests.v(76): (vlog- 2155) Global declarations are illegal in Verilog 2001 syntax. ** Error: E:/work/AC97/ac97_ctrl/bench/verilog/tests.v(103): Undefined variable: wb_busy. ** Error: E:/work/AC97/ac97_ctrl/bench/verilog/tests.v(104): Verilog Compiler exiting all others is OK,if u give me some suggestion i will be very happy. thank you very much! |
|||
|
the errors of "tests.v" module?
by Unknown on Sep 15, 2007 |
Not available! | ||
|
Are you trying to compile .h files too. Usually you get this error in
Modelsim when you try to compile .h files using vlog statement..
-- parag
----- Original Message -----
From: xinjianhong at 163.comxinjianhong at 1...>
To:
Date: Thu Sep 13 06:48:31 CEST 2007
Subject: [oc] the errors of "tests.v" module?
hi,
At first,thanks for your AC'97 source code. when I do the compile by Modelsim there is some errors with the "tests.v" file, I.E. ** Error: E:/work/AC97/ac97_ctrl/bench/verilog/tests.v(76): (vlog- 2155) Global declarations are illegal in Verilog 2001 syntax. ** Error: E:/work/AC97/ac97_ctrl/bench/verilog/tests.v(103): Undefined variable: wb_busy. ** Error: E:/work/AC97/ac97_ctrl/bench/verilog/tests.v(104): Verilog Compiler exiting all others is OK,if u give me some suggestion i will be very happy. thank you very much! |
|||
|
the errors of "tests.v" module?
by jinsongq on Dec 24, 2008 |
jinsongq
Posts: 1 Joined: May 24, 2009 Last seen: Oct 9, 2017 |
||
|
this situation also happen to me,
----- Original Message -----
From: xinjianhong at 163.comxinjianhong at 1...>
To:
Date: Thu Sep 13 06:48:31 CEST 2007
Subject: [oc] the errors of "tests.v" module?
hi,
At first,thanks for your AC'97 source code. when I do the compile by Modelsim there is some errors with the "tests.v" file, I.E. ** Error: E:/work/AC97/ac97_ctrl/bench/verilog/tests.v(76): (vlog- 2155) Global declarations are illegal in Verilog 2001 syntax. ** Error: E:/work/AC97/ac97_ctrl/bench/verilog/tests.v(103): Undefined variable: wb_busy. ** Error: E:/work/AC97/ac97_ctrl/bench/verilog/tests.v(104): Verilog Compiler exiting all others is OK,if u give me some suggestion i will be very happy. thank you very much! |
|||
|
RE: the errors of
by zxn on Apr 25, 2013 |
zxn
Posts: 1 Joined: Nov 27, 2011 Last seen: Apr 25, 2013 |
||
|
I met the same problem :
# Model Technology ModelSim SE vlog 10.1a Compiler 2012.02 Feb 22 2012 # ** Error: E:/NFC/micro_momory_module/NFC_V0_com_test_1gb/src/tb/env/nand_parameters.vh(58): (vlog-2155) Global declarations are illegal in Verilog 2001 syntax. # # ** Error: E:/NFC/micro_momory_module/NFC_V0_com_test_1gb/src/tb/env/nand_parameters.vh(120): (vlog-2730) Undefined variable: 'tWC_min'. # # ** Error: E:/NFC/micro_momory_module/NFC_V0_com_test_1gb/src/tb/env/nand_parameters.vh(120): 'tWC_min' already declared in this scope (work). # ** Error: E:/NFC/micro_momory_module/NFC_V0_com_test_1gb/src/tb/env/nand_parameters.vh(120): Verilog Compiler exiting # ** Error: D:/modeltech_10.1a/win32/vlog failed. Can you help me ? HOW to solve it? |
|||
1/1