Ordinary CPU use dual logic / binary logic 0 and 1. Multi Valued Logic use more than 2 values. According to Prof Moraga, Multi Valued Logic (MVL) CPU can run Operating System for Binary system using minimum as 0 and maximum as 1. The MVL can be manufactured using Silicon and Germanium (SiGe). Advantage of MVL: With 16 bit CPU, the flat memory address space is 43 Megabytes (16 x 16 x 16). Intel had released MVL based Flash RAM. Is there any plan to create MVL CPU project on Opencores.org? Thank you. _____________________________________________________________ = You want FREE web-based email ? = You want your own @qon.lao.net address?? = Then you want LaoNet's WebMail ! = Get it at http://webmail.lao.net !!

Short answer: No. The majority of projects on OpenCores target FPGAs, which can only build binary-logic structures (although some interesting work was done using genetic algorithms to create Xilinx bitstreams). Doing multi-level logic requires access to a fab, a fistful of PhDs, a boatload of analog designers, ability to do 4-5 trial tape-outs to get it to work, and a decent-sized team of software folks to write up a new tool flow for you. MVL is a more optimal use of silicon resources, but for the people with resources to tape out a chip, silicon is cheap. The biggest problem with 65nm is what to put in all that extra space you now have. Until we hit a wall with process shrinks, I suspect this one will remain squarely in the research category. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20070924/95105fa9/attachment.htm

On Sun, 23 Sep 2007, big one wrote:


Most current flash memories store more than one bit per cell to reduce
die size.



Not to answer for everyone, but I doubt it.

Although it would be possible to rewrite the resolution rules in VHDL to
allow for more than the generally accepted 9, it would be a lot of work
and the result would be a simulation model which would never see
siliicon.

Clint