I created a test bench ( waveforms ) using Waveformer lite that comes with Libero. I then ran pre - synthesis simulation to check that my program works correctly. Model sim was used to do the pre - - synthesis simulation ( one of the Libero tools ). I checked the wave form that was created by Model sim and found no errors in my program. I then used Synplify ( one of the Libero tools ) to do the synthesis. After that I ran the post - synthesis simulation using Model sim. I just wanted to check the waveform in Model sim whether my program still works correctly after the synthesis. But with a shock I found that all my signals in the waveform have the value X. My wave form is basically now just a collection of flat lines with the value X. I have no idea what caused this to happen. There is no warring or errors in the program. I would appreciate it if somebody could please help me. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20070928/bea4361e/attachment.htm

This is a fairly normal start for gate-level simulation. Start by checking your clocks and resets. Synchronous resets, in particular, cause problems in gate-level sim, esp. when used with gated clocks. And there won't be any warnings -- the simulator is doing exactly what it's supposed to do. :) On 9/27/07, Iwan Kruger 14345609 at sun.ac.za> wrote: -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20071001/7742e187/attachment.htm