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pseudo random generator verilog code source
by Unknown on Nov 12, 2007 |
Not available! | ||
|
----- Original Message -----
From: Victor Snesarev vnsnes at y...>
To: cores at o...
Date: Wed, 13 Aug 2003 02:18:17 -0700 (PDT)
Subject: RE: [oc] pseudo random generator verilog code source
http://vnsnes.freeshell.org/lfsr/index.shtml
Not sure how an 's' made it in front of 'html' in the
link at the bottom of the message.
-Victor
--- Renaux Jacky renaux.jacky at w...> wrote:
> Hi
> Victor could you resend your URL , the one
> you
> pointed out is not recongnized
>
> thanks
>
> //\\\\\
> |~ ~ |
> Jacky .. ( O O )
> ___________oOOo_____( )_____oOOo__
> |
> | Jacky RENAUX
> | email : renaux.jacky at w...
> | web :
> http://perso.wanadoo.fr/jacky.renaux
> | tel : (33) 06 86 90 65 83
> | Oooo
> |____________oooO___( )______
> ( ) ( /
> \ ) ) /
> \ ( (_/
> \_)
>
>
> -----Message d'origine-----
> De : owner-cores at o...
> [mailto:owner-cores at o...]De la
> part de ni_zhihong at s...
> Envoyé : mercredi 13 août 2003 0356
> À : vnsnes at y...; cores at o...
> Objet : Re: [oc] pseudo random generator
> verilog code source
>
>
>
>
> ----- Original Message -----
> From: Victor Snesarev vnsnes at y... >
> To: cores at o...
> Date: Thu, 19 Sep 2002 12:14:25 -0700 (PDT)
> Subject: Re: [oc] pseudo random generator
> verilog code source
>
>
> > I wrote up a webpage about using LSFRs > (Linear Shift
> Feedback Registers) for pseudo-random
> number
> generation during time off work, maybe it
> will help:
>
> http://vnsnes.freeshell.org/lfsr/index.shtm
> l
>
>
> A link to an old Altera LFSR core is at > the bottom of
> the page.
>
> Hope this helps.
>
> --- olupas at o... wrote:
> > Hi all,
> > > > This will generate only one new bit per > clock.
> > Maybe you need 32 new bits per clock,
> to send
> > over a network ...
> > > > A good starting point might be AN49 > from Altera.
> >
> > I was unable to find this on the web, > so I have
> > built my owns,
> > starting from there. > > > > Unfortunately, I cannot send the > sources
> > but I can help you with hints.
> >
> > Cheers,
> > Ovidiu Lupas.
> >
> >
> >
> > ----- Original Message -----
> > From: Marko Mlinar markom at o... >
> > To: cores at o...
> > Date: Thu, 19 Sep 2002 10:55:46 +0200
> > Subject: Re: [oc] pseudo random
> generator verilog
> > code source
> >
> >
> > > > Here: > > > > reg [31:0] poly; > > > > always @(posedge clk or posedge > reset_poly)
> > if (reset_poly) poly
> 32'hdeaddead;
> > else poly
> poly[17] ^
> > poly[4]};
> >
> > On Thursday 19 September 2002 09:54, > Dharmeshbhai
> > PATEL wrote:
> > > Hi list,
> > > > > > Does any one has an idea where i > can get the
> > verilog code
> > source
> > > for a pseudo random generator
> (number or signal)
> > ?
> > >
> > > Please let me know. > > > > > > Thanks in advance. > > > D.PATEL > > > > > > > > > > > > > ___________________________________________ > __________________ >
> >
> > > Exclusif: 75 euros remboursés sur
> le pack
> > eXtense Haut Débit
> > de Wanadoo !
> > > Vivez l'Internet sans contrainte en
> bénéficiant
> > d'un prix
> > "tout compris",
> --
> To unsubscribe from cores mailing list
> please visit
> http://www.opencores.org/mailinglists.shtml
>
>
> > > d'un forfait haut débit illimit?
> d'un accès
> > ADSL et d'un
> > Modem ADSL simple
> http://www.ifrance.com/_reloc/mail.exclusif
> > > ?installer ! Cliquez ici :
> >
> >
> > > |
|||
|
pseudo random generator verilog code source
by Unknown on Nov 13, 2007 |
Not available! | ||
|
I'd try the LFSR page from Wikipedia:
http://en.wikipedia.org/wiki/LFSR
There's sample code on the page, and at the bottom are links to tables of
maximal-length LFSRs of various periods.
On Nov 12, 2007 10:07 AM, engineer_mohammad_adnan at yahoo.com> wrote:
----- Original Message -----
From: Victor Snesarev vnsnes at y...>
To: cores at o...
Date: Wed, 13 Aug 2003 02:18:17 -0700 (PDT)
Subject: RE: [oc] pseudo random generator verilog code source
>
>
> http://vnsnes.freeshell.org/lfsr/index.shtml
>
> Not sure how an 's' made it in front of 'html' in the
> link at the bottom of the message.
>
> -Victor
>
> --- Renaux Jacky renaux.jacky at w...> wrote:
> Hi
> Victor could you resend your URL , the one
> you
> pointed out is not recongnized
>
> thanks
>
> //\\\\\
> |~ ~ |
> Jacky .. ( O O )
> ___________oOOo_____( )_____oOOo__
> |
> | Jacky RENAUX
> | email : renaux.jacky at w...
> | web :
> http://perso.wanadoo.fr/jacky.renaux
> | tel : (33) 06 86 90 65 83
> | Oooo
> |____________oooO___( )______
> ( ) ( /
> \ ) ) /
> \ ( (_/
> \_)
>
>
> -----Message d'origine-----
> De : owner-cores at o...
> [mailto:owner-cores at o...]De la
> part de ni_zhihong at s...
> Envoyé : mercredi 13 août 2003 0356
> À : vnsnes at y...; cores at o...
> Objet : Re: [oc] pseudo random generator
> verilog code source
>
>
>
>
> ----- Original Message -----
> From: Victor Snesarev vnsnes at y... >
> To: cores at o...
> Date: Thu, 19 Sep 2002 12:14:25 -0700 (PDT)
> Subject: Re: [oc] pseudo random generator
> verilog code source
>
> >
> > > > I wrote up a webpage about using LSFRs > (Linear Shift
> > Feedback Registers) for pseudo-random
> number
> > generation during time off work, maybe it
> will help:
> >
> http://vnsnes.freeshell.org/lfsr/index.shtm
> l
> >
> >
> > A link to an old Altera LFSR core is at > the bottom of
> > the page.
> >
> > Hope this helps.
> >
> > --- olupas at o... wrote:
> > Hi all,
> > > > This will generate only one new bit per > clock.
> > Maybe you need 32 new bits per clock,
> to send
> > over a network ...
> > > > A good starting point might be AN49 > from Altera.
> >
> > I was unable to find this on the web, > so I have
> > built my owns,
> > starting from there. > > > > Unfortunately, I cannot send the > sources
> > but I can help you with hints.
> >
> > Cheers,
> > Ovidiu Lupas.
> >
> >
> >
> > ----- Original Message -----
> > From: Marko Mlinar markom at o... >
> > To: cores at o...
> > Date: Thu, 19 Sep 2002 10:55:46 +0200
> > Subject: Re: [oc] pseudo random
> generator verilog
> > code source
> >
> > >
> > > > > > Here: > > > > > > reg [31:0] poly; > > > > > > always @(posedge clk or posedge > reset_poly)
> > > if (reset_poly) poly
> 32'hdeaddead;
> > > else poly
> poly[17] ^
> > poly[4]};
> > >
> > > On Thursday 19 September 2002 09:54, > Dharmeshbhai
> > PATEL wrote:
> > > Hi list,
> > > > > > Does any one has an idea where i > can get the
> > verilog code
> > > source
> > > for a pseudo random generator
> (number or signal)
> > ?
> > >
> > > Please let me know. > > > > > > Thanks in advance. > > > D.PATEL > > > > > > > > > > > > > > ___________________________________________ > __________________ >
> >
> > > Exclusif: 75 euros remboursés sur
> le pack
> > eXtense Haut Débit
-------------- next part --------------
An HTML attachment was scrubbed...
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> > > de Wanadoo !
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
> > > Vivez l'Internet sans contrainte en
> bénéficiant
> > d'un prix
> > > "tout compris",
> --
> To unsubscribe from cores mailing list
> please visit
> http://www.opencores.org/mailinglists.shtml
>
>
> > > d'un forfait haut débit illimit?
> d'un accès
> > ADSL et d'un
> > > Modem ADSL simple
> http://www.ifrance.com/_reloc/mail.exclusif
> > > ?installer ! Cliquez ici :
> > >
> > >
> > > > > |
|||
|
pseudo random generator verilog code source
by Unknown on Nov 14, 2007 |
Not available! | ||
|
ThereÂ’s an LFSR implementation on opencores as part of the generic_fifos
project.
You may want to check that one out as well.
Richard
_____
From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On
Behalf Of Guy Hutchison
Sent: Tuesday, November 13, 2007 7:00 PM
To: Discussion list about free open source IP cores
Subject: Re: [oc] pseudo random generator verilog code source
I'd try the LFSR page from Wikipedia:
http://en.wikipedia.org/wiki/LFSR
There's sample code on the page, and at the bottom are links to tables of
maximal-length LFSRs of various periods.
On Nov 12, 2007 10:07 AM, engineer_mohammad_adnan at yahoo.com> wrote:
----- Original Message -----
From: Victor Snesarev vnsnes at y...>
To: cores at o...
Date: Wed, 13 Aug 2003 02:18:17 -0700 (PDT)
Subject: RE: [oc] pseudo random generator verilog code source
http://vnsnes.freeshell.org/lfsr/index.shtml
Not sure how an 's' made it in front of 'html' in the
link at the bottom of the message.
-Victor
--- Renaux Jacky renaux.jacky at w...> wrote:
> Hi
> Victor could you resend your URL , the one
> you
> pointed out is not recongnized
>
> thanks
>
> //\\\\\
> |~ ~ |
> Jacky .. ( O O )
> ___________oOOo_____( )_____oOOo__
> |
> | Jacky RENAUX
> | email : renaux.jacky at w...
> | web :
> http://perso.wanadoo.fr/jacky.renaux
> | tel : (33) 06 86 90 65 83
> | Oooo
> |____________oooO___( )______
> ( ) ( /
> \ ) ) /
> \ ( (_/
> \_)
>
>
> -----Message d'origine-----
> De : owner-cores at o...
> [mailto:owner-cores at o...]De la
> part de ni_zhihong at s...
> Envoyé : mercredi 13 août 2003 0356
> À : vnsnes at y...; cores at o...
> Objet : Re: [oc] pseudo random generator
> verilog code source
>
>
>
>
> ----- Original Message -----
> From: Victor Snesarev vnsnes at y... >
> To: cores at o...
> Date: Thu, 19 Sep 2002 12:14:25 -0700 (PDT)
> Subject: Re: [oc] pseudo random generator
> verilog code source
>
>
> > I wrote up a webpage about using LSFRs > (Linear Shift
> Feedback Registers) for pseudo-random
> number
> generation during time off work, maybe it
> will help:
>
> http://vnsnes.freeshell.org/lfsr/index.shtm
> l
>
>
> A link to an old Altera LFSR core is at > the bottom of
> the page.
>
> Hope this helps.
>
> --- olupas at o... wrote:
> > Hi all,
> > > > This will generate only one new bit per > clock.
> > Maybe you need 32 new bits per clock,
> to send
> > over a network ...
> > > > A good starting point might be AN49 > from Altera.
> >
> > I was unable to find this on the web, > so I have
> > built my owns,
> > starting from there. > > > > Unfortunately, I cannot send the > sources
> > but I can help you with hints.
> >
> > Cheers,
> > Ovidiu Lupas.
> >
> >
> >
> > ----- Original Message -----
> > From: Marko Mlinar markom at o... >
> > To: cores at o...
> > Date: Thu, 19 Sep 2002 10:55:46 +0200
> > Subject: Re: [oc] pseudo random
> generator verilog
> > code source
> >
> >
> > > > Here: > > > > reg [31:0] poly; > > > > always @(posedge clk or posedge > reset_poly)
> > if (reset_poly) poly
> 32'hdeaddead;
> > else poly
> poly[17] ^
> > poly[4]};
> >
> > On Thursday 19 September 2002 09:54, > Dharmeshbhai
> > PATEL wrote:
> > > Hi list,
> > > > > > Does any one has an idea where i > can get the
> > verilog code
> > source
> > > for a pseudo random generator
> (number or signal)
> > ?
> > >
> > > Please let me know. > > > > > > Thanks in advance. > > > D.PATEL > > > > > > > > > > > > > ___________________________________________ > __________________ >
> >
> > > Exclusif: 75 euros remboursés sur
> le pack
> > eXtense Haut Débit
> > de Wanadoo !
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
-------------- next part --------------
An HTML attachment was scrubbed...
URL: http://www.opencores.org/forums.cgi/cores/attachments/20071114/70860261/attachment-0001.htm
> > > Vivez l'Internet sans contrainte en
> bénéficiant
> > d'un prix
> > "tout compris",
> --
> To unsubscribe from cores mailing list
> please visit
> http://www.opencores.org/mailinglists.shtml
>
>
> > > d'un forfait haut débit illimit?
> d'un accès
> > ADSL et d'un
> > Modem ADSL simple
> http://www.ifrance.com/_reloc/mail.exclusif
> > > ?installer ! Cliquez ici :
> >
> >
> > > |
|||
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