[Disclaimer: I am a total VCS newbie.]

In wb_dma/bench/verilog, I am invoking ...

vcsi test_bench_top.v wb_slv_model.v wb_mast_model.v \
+warn=none +lint=all +v2k +libext+.v +incdir+../../rtl/verilog+ -y ../../rtl/verilog +libverbose

A comparable invocation with icarus-verilog *appears* to
work, but with vcsi, I get [edited]:

Top Level Modules:
test
TimeScale is 1 ns / 10 ps
Error-[XMRE] Cross-module reference resolution error
Cross module resolution failed, token 'wb_wr1'. Originating module
'test'.
"tests.v", 1220:
m0.wb_wr1((32'hb0000000 + 8'h38), 4'hf, 32'b0);
Error-[XMRE] Cross-module reference resolution error
Cross module resolution failed, token 'wb_wr1'. Originating module
'test'.
"tests.v", 873:
m0.wb_wr1((32'hb0000000 + 8'h84), 4'hf, {chunk_sz, 16'h0fff});
[and many more of the same]

I *know* that it read the .v files with those task
definitions. Do the above error messages mean something to
you? Thanks for any help,

Will