Been trying a few ideas out on the wishbone bus, aiming to get the
BFM/L up and running in the next few weeks, commitments and 1/2 term
permitting.

But,

In the wishbone specification, fig 1-2, page 15.

The master module, just trying to clarify please,

Is the master dat_o bus a output of the master, and it connects to the
dat_i of any slave ?

Have never done a wishbone bus before , and this is one thing that
could lead to problems if I get it wrong at the start.

Is the master dat_o bus a output of the master, and it connects to the
dat_i of any slave ?
[rih] Yes, dat_o always connects to dat_i, independent of master or slave
core. The _o and _i denote transfer direction as seen from the core.

Richard

andrewm at opencores.org wrote: Yes. It connects to dat_i of *all* slaves on the bus segment. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266

Ta guys,

I was checking as the wishbone generator has things 'different'. I've
reported it as a bug, and I'll do my test bench as per the spec.