I tried searching the forums for this topic, but the search was not formatted correctly and Google gave me this error... Your search - /forums.cgi/cores test bench - did not match any documents. My question is about test benches. I don't see anything here specifically for test benches. Is this site exclusively about synthesizable code? In particular, I was looking for a model that would replace the digital interface of a Codec in my test bench. My FPGA will be controlling a Codec. If I write the model myself, then I am only verifying that I can write code to implement what I think is the interface. By using an existing model I would be performing an actual verification of my interface. Is there any interest here for having test bench models for various common interfaces? While researching this topic, I did find a site that seems to be all about chip models, http://www.freemodelfoundry.com They don't have a model of a Codec, but they do have one for an ADC which is half the job. They seem to be doing a very professional job so that their models are complete with timing information. I think that makes it a much harder job to construct new models. I am mainly interested in functional models rather than a full timing model. Rick -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20080215/58211ba9/attachment-0001.htm

I'm in the process of doing a BFM for the Wishbone bus, Andrew Mulcock -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of Rick Collins Sent: 15 February 2008 16:10 To: cores at opencores.org Subject: [oc] Test benches I tried searching the forums for this topic, but the search was not formatted correctly and Google gave me this error... Your search - /forums.cgi/cores test bench - did not match any documents. My question is about test benches. I don't see anything here specifically for test benches. Is this site exclusively about synthesizable code? In particular, I was looking for a model that would replace the digital interface of a Codec in my test bench. My FPGA will be controlling a Codec. If I write the model myself, then I am only verifying that I can write code to implement what I think is the interface. By using an existing model I would be performing an actual verification of my interface. Is there any interest here for having test bench models for various common interfaces? While researching this topic, I did find a site that seems to be all about chip models, HYPERLINK "http://www.freemodelfoundry.com/"http://www.freemodelfoundry.com They don't have a model of a Codec, but they do have one for an ADC which is half the job. They seem to be doing a very professional job so that their models are complete with timing information. I think that makes it a much harder job to construct new models. I am mainly interested in functional models rather than a full timing model. Rick No virus found in this incoming message. Checked by AVG Free Edition. Version: 7.5.516 / Virus Database: 269.20.6/1282 - Release Date: 15/02/2008 19:08 No virus found in this outgoing message. Checked by AVG Free Edition. Version: 7.5.516 / Virus Database: 269.20.6/1282 - Release Date: 15/02/2008 19:08 -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20080216/4d4fad43/attachment.html