1/1 
|
Some problems with wishbone simulation
by Unknown on Feb 18, 2008 |
Not available! | ||
|
hi,
when I was compiling the test.v file, which located in / wb_conmax / bench, with ModelSim 6.3c, it always reported a error " Global declarations are illegal in Verilog 2001 syntax." I have changed syntax to Verilog 1995, it still had this problem........ Thanks |
|||
1/1