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FPGA based Co-processor for reducing CPU burden on TCP/IP
by rickyjamesa on Mar 13, 2008 |
rickyjamesa
Posts: 3 Joined: Mar 11, 2008 Last seen: Jan 22, 2019 |
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Hi christoph,
Thank you for your response.
I have a solid experience on digital design and am entering into the
new field (Both hardware and embedded). I'm also looking for the free
IP cores so I could get a not-so-expensive prototyping. Can you
suggest me some?
Ricky
----- Original Message -----
From: Christoph Zimmermannnussgipfel at b...>
To:
Date: Tue Mar 11 22:05:57 CET 2008
Subject: [oc] FPGA based Co-processor for reducing CPU burden on
TCP/IP
processing
hi ricky
there are at least two companies out there with products and
services
to support your idea. also cray is selling a high performance
computing
system with such a combination.
http://www.drccomputer.com/drc/modules.html
http://www.xtremedatainc.com/index.php?option=com_content&view=article&id=102&Itemid=156
yes, anything closed and high priced.
if you had the idea to make an homebrew board for that, for get it.
hypertransport is to fast to make a simple board by your self. if
you
have a lot of experience with hardware design it's still possible
but
you need a lot of time and realy good tools to manage it.
what is your background? (software engineer, hardware engineer,
embedded developer,...)
greetings
christoph
Am Tue, 11 Mar 2008 01:37:19 -0700 (PDT)
schrieb Ricky James Allam :
> Hi All:
> > I am new in FPGA design and am currently doing a personal research
> project on how to implement a co-processor using
HyperTransport
> technology. The co-processor is to be used to reduce the
burden of
> the host CPU (AMD Opteron) in processing TCP/IP protocols.
> > Can you provide me some ideas on this to come up with a rough > prototype of the project? > > Your help is highly appreciated. > > Thanks a lot, > > Ricky > > > > ____________________________________________________________________________________
> Never miss a thing. Make Yahoo your home page.
> http://www.yahoo.com/r/hs
>
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
>
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FPGA based Co-processor for reducing CPU burden on TCP/IP
by rickyjamesa on Mar 13, 2008 |
rickyjamesa
Posts: 3 Joined: Mar 11, 2008 Last seen: Jan 22, 2019 |
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Hi Umair, thank you for the message. Is there a rough architecture
that you can suggest for me? I would be more interested in
implementing it on PCIe cards using the GMAC.
----- Original Message -----
From: Umair Siddiquiumairsiddiqui84 at g...>
To:
Date: Wed Mar 12 10:22:45 CET 2008
Subject: [oc] FPGA based Co-processor for reducing CPU burden on
TCP/IP
processing
hey man, for personal research I think check this
http://www.em.avnet.com/evk/home/0,4534,CID%253D7816%2526CCD%253DUSA%2526SID%253DNoNav%2526DID%253DDF2%2526LID%253DNoNav%25255F%2526BID%253DDF2%2526CTP%253DEVK,00.html
Avnet Spartan 3 board, it has 10/100 Ethernet MAC, and PCI (not
PCIe).
or some other board with similar facilities. (downside of this
board
that it contains 1 M SRAM, it should contain 64/128M SDRAM,
search different catalogs and try to get more gates and DRAM bits)
-You can attach it to your PC PCI slot.
-Both PCI and Ethernet MAC Cores are available on OpenCores
-the rest of the FPGA will contain your TOE logic.
and you also need to write the software driver of this board.
i think if you can do enough TOE with this much hardware and PCI
would
be more the enough for Packet DMA transfers.
On Wed, Mar 12, 2008 at 2:05 AM, Christoph Zimmermann
wrote:
http://www.xtremedatainc.com/index.php?option=com_content&view=article&id=102&Itemid=156
> hi ricky
> > there are at least two companies out there with products and services
> to support your idea. also cray is selling a high performance
computing
> system with such a combination.
> http://www.drccomputer.com/drc/modules.html
>
>
> yes, anything closed and high priced. > > if you had the idea to make an homebrew board for that, for get it.
> hypertransport is to fast to make a simple board by your self.
if you
> have a lot of experience with hardware design it's still
possible but
> you need a lot of time and realy good tools to manage it.
> > what is your background? (software engineer, hardware engineer,
> embedded developer,...)
>
> greetings
> christoph
>
> Am Tue, 11 Mar 2008 01:37:19 -0700 (PDT)
> schrieb Ricky James Allam :
>
>
>
> Hi All:
> > I am new in FPGA design and am currently doing a personal research
> project on how to implement a co-processor using
HyperTransport
> technology. The co-processor is to be used to reduce the
burden of
> the host CPU (AMD Opteron) in processing TCP/IP
protocols.
>
> Can you provide me some ideas on this to come up with a rough
> prototype of the project?
> > Your help is highly appreciated. > > Thanks a lot, > > Ricky > > > > ____________________________________________________________________________________
> Never miss a thing. Make Yahoo your home page.
> http://www.yahoo.com/r/hs
>
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
>
>
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
>
|
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FPGA based Co-processor for reducing CPU burden on TCP/IP
by UmairSiddiqui on Mar 13, 2008 |
UmairSiddiqui
Posts: 21 Joined: Aug 13, 2005 Last seen: Sep 19, 2016 |
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the cost of PCIe proto-board > the cost of PCI proto-board.
Well I need to heck the TOE arch...
After searching I found: (I don't have IEEE and springer account )
(1)
www.altera.com/literature/dc/3.3-2005_Taiwan_3rd_ChengKungU-web.pdf
(2)
http://ieeexplore.ieee.org/Xplore/login.jsp?url=/iel5/10886/34256/01633880.pdf?isnumber=34256&prod=CNF&arnumber=1633880&arSt=+160&ared=+166&arAuthor=+Tianhua+Liu%3B++Hongfeng+Zhu%3B++Chuansheng+Zhou%3B++Guiran+Chang
[qoute]
A New Method of TOE Architecture Based on the ML403 Development Board in Linux
Tianhua Liu; Hongfeng Zhu; Chuansheng Zhou; Guiran Chang
Computer and Computational Sciences, 2006. IMSCCS apos;06. First
International Multi-Symposiums on
Volume 2, Issue , 20-24 April 2006 Page(s): 160 - 166
Digital Object Identifier 10.1109/IMSCCS.2006.154
Summary: Purpose-to remove CPU from heavy services of protocol
processing, and alleviate the bottlenecks of communication system to
suit for the high speed network. Design a new architecture for TOE
which includes TOE design, TOE data stream transfer, TOE performance
test and TOE security, etc. Methodology-by analysis and design with
Linux specialties binding to functions of ML403 development version,
to code or modify portion of kernel code and use VHDL to design the
hardware section. Result-by analysis the design requirements of TCP/IP
offload, to simplify the protocol stack of TCP/IP, and finally to give
out a ML403 based solution for TOE architecture design, to build a
system experiment platform and last we draw some conclusions and some
test results. Conclusion-Although the results show that the
performance improving is not much, the simple success of test
indicates that this solution is correct and potential. It will
contribute to the performance improvement of whole communication
system and popularization to the TOE network card.
[/quote]
On Thu, Mar 13, 2008 at 9:35 AM, rickyjamesa at yahoo.com> wrote:
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
Hi Umair, thank you for the message. Is there a rough architecture
that you can suggest for me? I would be more interested in
implementing it on PCIe cards using the GMAC.
----- Original Message -----
From: Umair Siddiquiumairsiddiqui84 at g...>
To:
Date: Wed Mar 12 10:22:45 CET 2008
Subject: [oc] FPGA based Co-processor for reducing CPU burden on
TCP/IP
processing
> hey man, for personal research I think check this
http://www.em.avnet.com/evk/home/0,4534,CID%253D7816%2526CCD%253DUSA%2526SID%253DNoNav%2526DID%253DDF2%2526LID%253DNoNav%25255F%2526BID%253DDF2%2526CTP%253DEVK,00.html
> > >
>
> Avnet Spartan 3 board, it has 10/100 Ethernet MAC, and PCI (not > PCIe). > or some other board with similar facilities. (downside of this > board > that it contains 1 M SRAM, it should contain 64/128M SDRAM, > search different catalogs and try to get more gates and DRAM bits) > -You can attach it to your PC PCI slot. > -Both PCI and Ethernet MAC Cores are available on OpenCores > -the rest of the FPGA will contain your TOE logic. > and you also need to write the software driver of this board. > i think if you can do enough TOE with this much hardware and PCI > would > be more the enough for Packet DMA transfers.
> On Wed, Mar 12, 2008 at 2:05 AM, Christoph Zimmermann
> wrote:
http://www.xtremedatainc.com/index.php?option=com_content&view=article&id=102&Itemid=156
> > hi ricky
> > > > there are at least two companies out there with products and > services
> > to support your idea. also cray is selling a high performance
> computing
> > system with such a combination.
> > http://www.drccomputer.com/drc/modules.html
> >
>
> >
> > yes, anything closed and high priced. > > > > if you had the idea to make an homebrew board for that, for > get it.
> > hypertransport is to fast to make a simple board by your self.
> if you
> > have a lot of experience with hardware design it's still
> possible but
> > you need a lot of time and realy good tools to manage it.
> > > > what is your background? (software engineer, hardware > engineer,
> > embedded developer,...)
> >
> > greetings
> > christoph
> >
> > Am Tue, 11 Mar 2008 01:37:19 -0700 (PDT)
> > schrieb Ricky James Allam :
> >
> >
> >
> > Hi All:
> > > > I am new in FPGA design and am currently doing a personal > research
> > project on how to implement a co-processor using
> HyperTransport
> > technology. The co-processor is to be used to reduce the
> burden of
> > the host CPU (AMD Opteron) in processing TCP/IP
> protocols.
> >
> > Can you provide me some ideas on this to come up with a > rough
> > prototype of the project?
> > > > Your help is highly appreciated. > > > > Thanks a lot, > > > > Ricky > > > > > > > > > ____________________________________________________________________________________
> > Never miss a thing. Make Yahoo your home page.
> > http://www.yahoo.com/r/hs
> >
> > _______________________________________________
> > http://www.opencores.org/mailman/listinfo/cores
> >
> >
> > _______________________________________________
> > http://www.opencores.org/mailman/listinfo/cores
> >
> > |
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FPGA based Co-processor for reducing CPU burden on TCP/IP
by rickyjamesa on Mar 13, 2008 |
rickyjamesa
Posts: 3 Joined: Mar 11, 2008 Last seen: Jan 22, 2019 |
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Hi Nathan,
Xilinx ISE allows the combination of module files written in either
verilog or VHDL. If you add modules, there is an option for you to
select the appropriate language.
There are also available tools for you convert code from Verilog to
VHDL, try this script: http://www.taudelta.com.au/v2vhd.html
Hope you can provide me some reference design too, i am interested to
your experiment.
Thanks,
Ricky
----- Original Message -----
From: Nathan Williamsngwilliams at g...>
To:
Date: Thu Mar 13 06:26:45 CET 2008
Subject: [oc] FPGA based Co-processor for reducing CPU burden on
TCP/IP
processing
>
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
>
Does the PCI core on OpenCores support DMA? I don't have any
Verilog
experience, only some VHDL. I have this Avnet PCI development board
and am trying to make a PCI interface for an ADSL modem chipset.
Regards,
Nathan
On 12/03/2008, Umair Siddiqui
wrote:
http://www.em.avnet.com/evk/home/0,4534,CID%253D7816%2526CCD%253DUSA%2526SID%253DNoNav%2526DID%253DDF2%2526LID%253DNoNav%25255F%2526BID%253DDF2%2526CTP%253DEVK,00.html
> hey man, for personal research I think check this
> >
>
> Avnet Spartan 3 board, it has 10/100 Ethernet MAC, and PCI (not PCIe).
> or some other board with similar facilities. (downside of this
board
> that it contains 1 M SRAM, it should contain 64/128M SDRAM,
> search different catalogs and try to get more gates and DRAM bits)
>
> -You can attach it to your PC PCI slot. > -Both PCI and Ethernet MAC Cores are available on OpenCores > -the rest of the FPGA will contain your TOE logic. > > and you also need to write the software driver of this board. > > i think if you can do enough TOE with this much hardware and PCI would
> be more the enough for Packet DMA transfers.
>
>
>
>
>
>
>
>
>
>
>
>
> On Wed, Mar 12, 2008 at 2:05 AM, Christoph Zimmermann
> wrote:
http://www.xtremedatainc.com/index.php?option=com_content&view=article&id=102&Itemid=156
> hi ricky
> > there are at least two companies out there with products and services
> to support your idea. also cray is selling a high
performance computing
> system with such a combination.
> http://www.drccomputer.com/drc/modules.html
>
>
> yes, anything closed and high priced. > > if you had the idea to make an homebrew board for that, for get it.
> hypertransport is to fast to make a simple board by your
self. if you
> have a lot of experience with hardware design it's still
possible but
> you need a lot of time and realy good tools to manage it.
> > what is your background? (software engineer, hardware engineer,
> embedded developer,...)
> > greetings > christoph > > Am Tue, 11 Mar 2008 01:37:19 -0700 (PDT) > schrieb Ricky James Allam yahoo.com>:
>
> >
> > Hi All:
> > > > I am new in FPGA design and am currently doing a personal research
> > project on how to implement a co-processor using
HyperTransport
> > technology. The co-processor is to be used to reduce
the burden of
> > the host CPU (AMD Opteron) in processing TCP/IP
protocols.
> >
> > Can you provide me some ideas on this to come up with a rough
> > prototype of the project?
> > > > Your help is highly appreciated. > > > > Thanks a lot, > > > > Ricky > > > > > > > > ____________________________________________________________________________________
> > Never miss a thing. Make Yahoo your home page.
> > http://www.yahoo.com/r/hs
> >
> > _______________________________________________
> > http://www.opencores.org/mailman/listinfo/cores
> >
>
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
>
|
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FPGA based Co-processor for reducing CPU burden on TCP/IP
by Unknown on Apr 23, 2008 |
Not available! | ||
|
----- Original Message -----
From: H. Peter Anvinhpa at z...>
To:
Date: Sat Apr 5 03:44:28 CEST 2008
Subject: [oc] FPGA based Co-processor for reducing CPU burden on
TCP/IP
processing
Ricky James Allam wrote:
The author might be thinking to include other functionality not just
simply an "offloader", like the Tarari's accelerators:
http://en.wikipedia.org/wiki/Tarari
> Hi All:
> > I am new in FPGA design and am currently doing a personal research project on how to implement a co-processor using HyperTransport technology. The co-processor is to be used to reduce the burden of the host CPU (AMD Opteron) in processing TCP/IP protocols.
>
> Can you provide me some ideas on this to come up with a rough prototype of the project?
>
> Your help is highly appreciated. > I hate to say it, but it probably makes more sense to integrate the network interface -- both to reduce memory bandwidth and give you more direct control over it. At that point, you're a TOE Ethernet card. -hpa |
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