1/1 
|
Integrate I2C core into FPGA
by Unknown on Mar 26, 2008 |
Not available! | ||
|
I'm currently working on a senior project (EE undergrad) where one of
the requirements is to replace an existing I2C chip with a coded version of the I2C loaded directly onto the FPGA. I really want to use the I2C core from this site written by Richard Herveille, but I'm really confused about how the whole wishbone thing works. The system the I2C is interfaced with is very simple. Overall, the device is a camera. I have a KODAK board (imaging sensor) connected to a board that contains all the electrical components (RAM, FPGA: XCV300-4PQ240C in PQFP 240 pin package, USB DLP chip, I2C chip) which connects to a computer via the USB port. Matlab owns the whole process, there are 2 files written that write the KODAK registers and the reads them (for verification) over the I2C chip. I've had to reverse engineer the project, I was given a prototype, told to figure it out by building the whole thing from the ground up, and then make the changes per requirements. Currently, there is a statemachine in the VHDL code that evenutally outputs received signals from the FPGA to the I2C chip. The only pins hooked up as outputs of the FPGA to inputs of the I2C chip are: A0, A1, WT', RD' CE', and RST'. D0-D7 (8-bit data line) is hooked up to the I2C as bi-directional data. Finally, I have the SCL and SDA lines hooked up to the Kodak board. My idea was to redefine the outputs of the FPGA as internal signals that would map to the I2C core signals. I think that the clock everything is running off of needs to be mapped to the clock signal in the I2C core as well. I know I'm asking for a whole lot of help here, but I'm really running out of places to turn to. thanks |
|||
|
Integrate I2C core into FPGA
by Unknown on Mar 26, 2008 |
Not available! | ||
|
Wishbone first.
Wishbone is a 'computer bus' inside the FPGA with master and peripherals (
slaves ).
Think of an address bus and a data bus. On a PC the data would be bi
directional, with tri state drivers on each peripheral.
As FPGA's don't support bi directional bus's the data bus is split into two
one from master, one too master.
As FPGA's don't tend to support internal tri state bus's, then 'and' gates
are used.
take the output of all the peripherals, and 'and' them together.
The 'trick' is to make certain the output of all but the peripheral
you want is set at zero,
I guess you currently have a 'Philips' parallel to I2C chip, PCF8584. which
is what you want to replace.
you might want to take a look here to get a handle on the chip your
trying to replace.
http://www.ai.rug.nl/~pave/i2c/i2c_to_parallel_port_text.html#pcf8584
-----Original Message-----
From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On
Behalf Of dslaman0877 at yahoo.com
Sent: 26 March 2008 18:12
To: cores at opencores.org
Subject: [oc] Integrate I2C core into FPGA
I'm currently working on a senior project (EE undergrad) where one of
the requirements is to replace an existing I2C chip with a coded version
of the I2C loaded directly onto the FPGA. I really want to use the I2C
core from this site written by Richard Herveille, but I'm really confused
about how the whole wishbone thing works.
The system the I2C is interfaced with is very simple. Overall, the
device is a camera. I have a KODAK board (imaging sensor) connected
to a board that contains all the electrical components (RAM, FPGA:
XCV300-4PQ240C in PQFP 240 pin package, USB DLP chip, I2C chip)
which connects to a computer via the USB port. Matlab owns the
whole process, there are 2 files written that write the KODAK registers
and the reads them (for verification) over the I2C chip.
I've had to reverse engineer the project, I was given a prototype, told
to figure it out by building the whole thing from the ground up, and then
make the changes per requirements.
Currently, there is a statemachine in the VHDL code that evenutally
outputs received signals from the FPGA to the I2C chip. The only pins
hooked up as outputs of the FPGA to inputs of the I2C chip are: A0, A1,
WT', RD' CE', and RST'. D0-D7 (8-bit data line) is hooked up to the I2C
as bi-directional data. Finally, I have the SCL and SDA lines hooked up
to the Kodak board.
My idea was to redefine the outputs of the FPGA as internal signals that
would map to the I2C core signals. I think that the clock everything is
running off of needs to be mapped to the clock signal in the I2C core as
well. I know I'm asking for a whole lot of help here, but I'm really
running out of places to turn to. thanks
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
No virus found in this incoming message.
Checked by AVG.
Version: 7.5.519 / Virus Database: 269.22.0/1343 - Release Date: 25/03/2008
19:17
No virus found in this outgoing message.
Checked by AVG.
Version: 7.5.519 / Virus Database: 269.22.0/1343 - Release Date: 25/03/2008
19:17
|
|||
|
Integrate I2C core into FPGA
by Unknown on Mar 26, 2008 |
Not available! | ||
|
Q1: Are you looking for an I2C master or slave? Who drives the SCL signal?
Richard
-----Original Message-----
From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On
Behalf Of dslaman0877 at yahoo.com
Sent: 26 March 2008 19:12
To: cores at opencores.org
Subject: [oc] Integrate I2C core into FPGA
I'm currently working on a senior project (EE undergrad) where one of
the requirements is to replace an existing I2C chip with a coded version
of the I2C loaded directly onto the FPGA. I really want to use the I2C
core from this site written by Richard Herveille, but I'm really confused
about how the whole wishbone thing works.
The system the I2C is interfaced with is very simple. Overall, the
device is a camera. I have a KODAK board (imaging sensor) connected
to a board that contains all the electrical components (RAM, FPGA:
XCV300-4PQ240C in PQFP 240 pin package, USB DLP chip, I2C chip)
which connects to a computer via the USB port. Matlab owns the
whole process, there are 2 files written that write the KODAK registers
and the reads them (for verification) over the I2C chip.
I've had to reverse engineer the project, I was given a prototype, told
to figure it out by building the whole thing from the ground up, and then
make the changes per requirements.
Currently, there is a statemachine in the VHDL code that evenutally
outputs received signals from the FPGA to the I2C chip. The only pins
hooked up as outputs of the FPGA to inputs of the I2C chip are: A0, A1,
WT', RD' CE', and RST'. D0-D7 (8-bit data line) is hooked up to the I2C
as bi-directional data. Finally, I have the SCL and SDA lines hooked up
to the Kodak board.
My idea was to redefine the outputs of the FPGA as internal signals that
would map to the I2C core signals. I think that the clock everything is
running off of needs to be mapped to the clock signal in the I2C core as
well. I know I'm asking for a whole lot of help here, but I'm really
running out of places to turn to. thanks
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
|
|||
|
Integrate I2C core into FPGA
by Unknown on Mar 27, 2008 |
Not available! | ||
|
Based on a previous post, I'm trying to replace the Phillips I2C: PCA9564
chip with your VHDL code.
Currently, the I2C phillips processor is the master.
If I can ever integrate the I2C function into the FPGA, the FPGA will be
the master. I don't know if this will help, but if you want to contact me
via email, maybe this process can run a little faster? I'm sure the forum
exists to help other people out with the same problems, but I'm thinking
email might work faster. I found out yesterday that I only have about 2
weeks to get this thing done, I couldn't even go to sleep last night I
was so stressed out. If everybody interested in helping out is ok with
that: jimbobsmit at gmail.com
That's a pseudo email I created to post on the internet so my real email
doesn't get flooded with spam or what not. I really don't want to step
on anybodies toes though, so if this isn't cool, that's fine, we can do
this through the forum.
thanks, dan
----- Original Message -----
From: Richard Herveillerichard at h...>
To:
Date: Wed Mar 26 23:10:13 CET 2008
Subject: [oc] Integrate I2C core into FPGA
Q1: Are you looking for an I2C master or slave? Who drives the SCL
signal?
Richard
-----Original Message-----
From: cores-bounces at opencores.org [mailto:cores-bounces at
opencores.org] On
Behalf Of dslaman0877 at yahoo.com
Sent: 26 March 2008 19:12
To: cores at opencores.org
Subject: [oc] Integrate I2C core into FPGA
I'm currently working on a senior project (EE undergrad) where one
of
the requirements is to replace an existing I2C chip with a coded
version
of the I2C loaded directly onto the FPGA. I really want to use the
I2C
core from this site written by Richard Herveille, but I'm really
confused
about how the whole wishbone thing works.
The system the I2C is interfaced with is very simple. Overall, the
device is a camera. I have a KODAK board (imaging sensor) connected
to a board that contains all the electrical components (RAM, FPGA:
XCV300-4PQ240C in PQFP 240 pin package, USB DLP chip, I2C chip)
which connects to a computer via the USB port. Matlab owns the
whole process, there are 2 files written that write the KODAK
registers
and the reads them (for verification) over the I2C chip.
I've had to reverse engineer the project, I was given a prototype,
told
to figure it out by building the whole thing from the ground up,
and then
make the changes per requirements.
Currently, there is a statemachine in the VHDL code that evenutally
outputs received signals from the FPGA to the I2C chip. The only
pins
hooked up as outputs of the FPGA to inputs of the I2C chip are: A0,
A1,
WT', RD' CE', and RST'. D0-D7 (8-bit data line) is hooked up to the
I2C
as bi-directional data. Finally, I have the SCL and SDA lines
hooked up
to the Kodak board.
My idea was to redefine the outputs of the FPGA as internal signals
that
would map to the I2C core signals. I think that the clock
everything is
running off of needs to be mapped to the clock signal in the I2C
core as
well. I know I'm asking for a whole lot of help here, but I'm
really
running out of places to turn to. thanks
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
|
|||
|
Integrate I2C core into FPGA
by Unknown on Mar 28, 2008 |
Not available! | ||
|
Guess was close, but off by a couple digits: PCA9564. I have the data
sheet, and I would say I have an OK understanding of it's operation.
Thank you very much for that explanation, it is very helpful. I've only
been able to find one person that's even heard of the wishbone protocol
and it ended there, he had only heard of it. But that explanation helps
make sense out of the code. Even though it's not the same chip, the
link helps too.
----- Original Message -----
From: andrew mulcockspam at m...>
To:
Date: Wed Mar 26 21:16:17 CET 2008
Subject: [oc] Integrate I2C core into FPGA
Wishbone first.
Wishbone is a 'computer bus' inside the FPGA with master and peripherals ( slaves ). Think of an address bus and a data bus. On a PC the data would be bi directional, with tri state drivers on each peripheral. As FPGA's don't support bi directional bus's the data bus is split into two one from master, one too master. As FPGA's don't tend to support internal tri state bus's, then 'and' gates are used. take the output of all the peripherals, and 'and' them together. The 'trick' is to make certain the output of all but the peripheral you want is set at zero, I guess you currently have a 'Philips' parallel to I2C chip, PCF8584. which is what you want to replace. you might want to take a look here to get a handle on the chip
your
http://www.ai.rug.nl/~pave/i2c/i2c_to_parallel_port_text.html#pcf8584
trying to replace.
-----Original Message-----
From: cores-bounces at opencores.org [mailto:cores-bounces at
opencores.org] On
Behalf Of dslaman0877 at yahoo.com
Sent: 26 March 2008 18:12
To: cores at opencores.org
Subject: [oc] Integrate I2C core into FPGA
I'm currently working on a senior project (EE undergrad) where one
of
the requirements is to replace an existing I2C chip with a coded
version
of the I2C loaded directly onto the FPGA. I really want to use the
I2C
core from this site written by Richard Herveille, but I'm really
confused
about how the whole wishbone thing works.
The system the I2C is interfaced with is very simple. Overall, the
device is a camera. I have a KODAK board (imaging sensor) connected
to a board that contains all the electrical components (RAM, FPGA:
XCV300-4PQ240C in PQFP 240 pin package, USB DLP chip, I2C chip)
which connects to a computer via the USB port. Matlab owns the
whole process, there are 2 files written that write the KODAK
registers
and the reads them (for verification) over the I2C chip.
I've had to reverse engineer the project, I was given a prototype,
told
to figure it out by building the whole thing from the ground up,
and then
make the changes per requirements.
Currently, there is a statemachine in the VHDL code that evenutally
outputs received signals from the FPGA to the I2C chip. The only
pins
hooked up as outputs of the FPGA to inputs of the I2C chip are: A0,
A1,
WT', RD' CE', and RST'. D0-D7 (8-bit data line) is hooked up to the
I2C
as bi-directional data. Finally, I have the SCL and SDA lines
hooked up
to the Kodak board.
My idea was to redefine the outputs of the FPGA as internal signals
that
would map to the I2C core signals. I think that the clock
everything is
running off of needs to be mapped to the clock signal in the I2C
core as
well. I know I'm asking for a whole lot of help here, but I'm
really
running out of places to turn to. thanks
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
No virus found in this incoming message.
Checked by AVG.
Version: 7.5.519 / Virus Database: 269.22.0/1343 - Release Date:
25/03/2008
19:17
No virus found in this outgoing message.
Checked by AVG.
Version: 7.5.519 / Virus Database: 269.22.0/1343 - Release Date:
25/03/2008
19:17
|
|||
|
Integrate I2C core into FPGA
by Unknown on Mar 28, 2008 |
Not available! | ||
|
Get a hold of the Wisbone SoC Interconnect document.
It is posted on the opencores website.
Wishbone is a pretty straightforward interconnect.
Most of the names should be self explanatory.
The i2c master provided on opencores should do just fine what you need.
However it is only an i2c interface. It requires a controller (statemachine,
cpu, whatever) to program the i2c master.
Richard
-----Original Message-----
From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On
Behalf Of dslaman0877 at yahoo.com
Sent: 28 March 2008 00:40
To: cores at opencores.org
Subject: Re: [oc] Integrate I2C core into FPGA
Guess was close, but off by a couple digits: PCA9564. I have the data
sheet, and I would say I have an OK understanding of it's operation.
Thank you very much for that explanation, it is very helpful. I've only
been able to find one person that's even heard of the wishbone protocol
and it ended there, he had only heard of it. But that explanation helps
make sense out of the code. Even though it's not the same chip, the
link helps too.
----- Original Message -----
From: andrew mulcockspam at m...>
To:
Date: Wed Mar 26 21:16:17 CET 2008
Subject: [oc] Integrate I2C core into FPGA
Wishbone first.
Wishbone is a 'computer bus' inside the FPGA with master and peripherals ( slaves ). Think of an address bus and a data bus. On a PC the data would be bi directional, with tri state drivers on each peripheral. As FPGA's don't support bi directional bus's the data bus is split into two one from master, one too master. As FPGA's don't tend to support internal tri state bus's, then 'and' gates are used. take the output of all the peripherals, and 'and' them together. The 'trick' is to make certain the output of all but the peripheral you want is set at zero, I guess you currently have a 'Philips' parallel to I2C chip, PCF8584. which is what you want to replace. you might want to take a look here to get a handle on the chip
your
http://www.ai.rug.nl/~pave/i2c/i2c_to_parallel_port_text.html#pcf8584
trying to replace.
-----Original Message-----
From: cores-bounces at opencores.org [mailto:cores-bounces at
opencores.org] On
Behalf Of dslaman0877 at yahoo.com
Sent: 26 March 2008 18:12
To: cores at opencores.org
Subject: [oc] Integrate I2C core into FPGA
I'm currently working on a senior project (EE undergrad) where one
of
the requirements is to replace an existing I2C chip with a coded
version
of the I2C loaded directly onto the FPGA. I really want to use the
I2C
core from this site written by Richard Herveille, but I'm really
confused
about how the whole wishbone thing works.
The system the I2C is interfaced with is very simple. Overall, the
device is a camera. I have a KODAK board (imaging sensor) connected
to a board that contains all the electrical components (RAM, FPGA:
XCV300-4PQ240C in PQFP 240 pin package, USB DLP chip, I2C chip)
which connects to a computer via the USB port. Matlab owns the
whole process, there are 2 files written that write the KODAK
registers
and the reads them (for verification) over the I2C chip.
I've had to reverse engineer the project, I was given a prototype,
told
to figure it out by building the whole thing from the ground up,
and then
make the changes per requirements.
Currently, there is a statemachine in the VHDL code that evenutally
outputs received signals from the FPGA to the I2C chip. The only
pins
hooked up as outputs of the FPGA to inputs of the I2C chip are: A0,
A1,
WT', RD' CE', and RST'. D0-D7 (8-bit data line) is hooked up to the
I2C
as bi-directional data. Finally, I have the SCL and SDA lines
hooked up
to the Kodak board.
My idea was to redefine the outputs of the FPGA as internal signals
that
would map to the I2C core signals. I think that the clock
everything is
running off of needs to be mapped to the clock signal in the I2C
core as
well. I know I'm asking for a whole lot of help here, but I'm
really
running out of places to turn to. thanks
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
No virus found in this incoming message.
Checked by AVG.
Version: 7.5.519 / Virus Database: 269.22.0/1343 - Release Date:
25/03/2008
19:17
No virus found in this outgoing message.
Checked by AVG.
Version: 7.5.519 / Virus Database: 269.22.0/1343 - Release Date:
25/03/2008
19:17
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
|
|||
|
Integrate I2C core into FPGA
by Unknown on Apr 4, 2008 |
Not available! | ||
|
OK, it's been a couple days and I've been doing some studying on this.
I still have some questions though that I'm sure can be answered.
Question 1:
wb_clk_i - the way I currently interface with the Phillips i2c chip is by
setting the clock frequency (CR[2:0] =101) to 59kHz. I chose this
value based on the data sheet saying, essentially, this is the most
stable operating frequency that the chip will kick out at. The SCL line
connected to my slave operates between 0-400 kHz. So, my main
circuit board is operating at a 12MHz rate, so to set up the wb_clk_i, I
used this equation: wb_clk_i = (12MHz)/(4*59kHz) -1 = 39.677 (dec).
So I don't get a whole number, is this a problem? I'm leaning towards
thinking that I'm not restricted at by the Phillips chip anymore, so I
should be able to choose any frequency between 0-400 kHz to replace
59kHz with that results in a whole number and the system should work
fine...did any of this make any sense?
Question 2:
I'm pretty sure I know the answer to this one, but it's best to make
sure. It looks like this i2c core behaves very similar to the Phillips
pca9564 chip that I have. The way I've got my code written in matlab,
I set the chip to master transmit mode and then I have a loop written
where I read the status register until I see ox08 (the start was
transmitted). This I2C core retains that sort of information, right? It
looks like it returns one bit back to the status register (for ack), so it
looks like I'll have to change all my hex values to read from. but I'll still
be able to read the status register right?
Question 3: In the i2c_master_top.vhd module, the assign wb_dat_o
process (~line 188), why are the addresses 000 and 001 assigned
values as though a 32 bit data stream came in? I don't know if it's very
important, but it's very confusing to me why that happens.
I'd like to say, this i2c code take s a while for an amateur (me) to figure
out, but it's very elegant code once you start to grasp it. Thumbs up
to Mr. H. Very nice.
I'll definitely have more questions later, thanks in advance for
everyoneÂ’s time.
----- Original Message -----
From: Richard Herveillerichard at h...>
To:
Date: Fri Mar 28 16:07:15 CET 2008
Subject: [oc] Integrate I2C core into FPGA
Get a hold of the Wisbone SoC Interconnect document.
It is posted on the opencores website.
Wishbone is a pretty straightforward interconnect.
Most of the names should be self explanatory.
The i2c master provided on opencores should do just fine what you
need.
However it is only an i2c interface. It requires a controller
(statemachine,
cpu, whatever) to program the i2c master.
Richard
-----Original Message-----
From: cores-bounces at opencores.org [mailto:cores-bounces at
opencores.org] On
Behalf Of dslaman0877 at yahoo.com
Sent: 28 March 2008 00:40
To: cores at opencores.org
Subject: Re: [oc] Integrate I2C core into FPGA
Guess was close, but off by a couple digits: PCA9564. I have the
data
sheet, and I would say I have an OK understanding of it's
operation.
Thank you very much for that explanation, it is very helpful. I've
only
been able to find one person that's even heard of the wishbone
protocol
and it ended there, he had only heard of it. But that explanation
helps
make sense out of the code. Even though it's not the same chip, the
link helps too.
----- Original Message -----
From: andrew mulcock
To:
Date: Wed Mar 26 21:16:17 CET 2008
Subject: [oc] Integrate I2C core into FPGA
http://www.ai.rug.nl/~pave/i2c/i2c_to_parallel_port_text.html#pcf8584
> Wishbone first.
> > Wishbone is a 'computer bus' inside the FPGA with master and > peripherals ( > slaves ). > > Think of an address bus and a data bus. On a PC the data would be
> bi
> directional, with tri state drivers on each peripheral. > As FPGA's don't support bi directional bus's the data bus is split
> into two
> one from master, one too master. > As FPGA's don't tend to support internal tri state bus's, then > 'and' gates > are used. > take the output of all the peripherals, and 'and' them together.
> The 'trick' is to make certain the output of all but the
> peripheral > you want is set at zero, > I guess you currently have a 'Philips' parallel to I2C chip, > PCF8584. which > is what you want to replace. > you might want to take a look here to get a handle on the chip
> your
> trying to replace. > > >
> -----Original Message-----
> From: cores-bounces at opencores.org [mailto:cores-bounces at > opencores.org] On > Behalf Of dslaman0877 at yahoo.com > Sent: 26 March 2008 18:12 > To: cores at opencores.org > Subject: [oc] Integrate I2C core into FPGA > I'm currently working on a senior project (EE undergrad) where one
> of
> the requirements is to replace an existing I2C chip with a coded
> version
> of the I2C loaded directly onto the FPGA. I really want to use the
> I2C
> core from this site written by Richard Herveille, but I'm really
> confused
> about how the whole wishbone thing works. > The system the I2C is interfaced with is very simple. Overall, the
> device is a camera. I have a KODAK board (imaging sensor)
connected
> to a board that contains all the electrical components (RAM,
FPGA:
> XCV300-4PQ240C in PQFP 240 pin package, USB DLP chip, I2C
chip)
> which connects to a computer via the USB port. Matlab owns the
> whole process, there are 2 files written that write the KODAK > registers > and the reads them (for verification) over the I2C chip. > I've had to reverse engineer the project, I was given a prototype,
> told
> to figure it out by building the whole thing from the ground up,
> and then
> make the changes per requirements. > Currently, there is a statemachine in the VHDL code that evenutally
> outputs received signals from the FPGA to the I2C chip. The
only
> pins
> hooked up as outputs of the FPGA to inputs of the I2C chip are: A0,
> A1,
> WT', RD' CE', and RST'. D0-D7 (8-bit data line) is hooked up to the > I2C > as bi-directional data. Finally, I have the SCL and SDA lines > hooked up > to the Kodak board. > My idea was to redefine the outputs of the FPGA as internal signals
> that > would map to the I2C core signals. I think that the
clock > everything is > running off of needs to be mapped to
the clock signal in the I2C > core as > well. I know I'm
asking for a whole lot of help here, but I'm > really >
running out of places to turn to. thanks >
_______________________________________________ >
http://www.opencores.org/mailman/listinfo/cores > No virus found
in this incoming message. > Checked by AVG. > Version:
7.5.519 / Virus Database: 269.22.0/1343 - Release Date: >
25/03/2008 > 19:17 > No virus found in this outgoing message.
> Checked by AVG. > Version: 7.5.519 / Virus Database:
269.22.0/1343 - Release Date: > 25/03/2008 > 19:17 > >
> _______________________________________________
http://www.opencores.org/mailman/listinfo/cores
|
|||
|
Integrate I2C core into FPGA
by Unknown on Apr 6, 2008 |
Not available! | ||
|
Question 1:
wb_clk_i - the way I currently interface with the Phillips i2c chip is by
setting the clock frequency (CR[2:0] =101) to 59kHz. I chose this
value based on the data sheet saying, essentially, this is the most
stable operating frequency that the chip will kick out at. The SCL line
connected to my slave operates between 0-400 kHz. So, my main
circuit board is operating at a 12MHz rate, so to set up the wb_clk_i, I
used this equation: wb_clk_i = (12MHz)/(4*59kHz) -1 = 39.677 (dec).
So I don't get a whole number, is this a problem? I'm leaning towards
thinking that I'm not restricted at by the Phillips chip anymore, so I
should be able to choose any frequency between 0-400 kHz to replace
59kHz with that results in a whole number and the system should work
fine...did any of this make any sense?
[rih] Yes makes sense.
I think the actual calculation would be 12MHz/(5*59kHz) ...
This value is programmed into the clock control register. Which basically
loads a counter with the programmed value.
Each time the counter turns '0' an internal pulse is generated which clocks
the bit controller statemachine.
I would round 39 up to 40, which results in a slightly slower frequency.
Question 2:
I'm pretty sure I know the answer to this one, but it's best to make
sure. It looks like this i2c core behaves very similar to the Phillips
pca9564 chip that I have. The way I've got my code written in matlab,
I set the chip to master transmit mode and then I have a loop written
where I read the status register until I see ox08 (the start was
transmitted). This I2C core retains that sort of information, right? It
looks like it returns one bit back to the status register (for ack), so it
looks like I'll have to change all my hex values to read from. but I'll
still
be able to read the status register right?
[rih] The different hex values are caused by different arrangement of bits
in the control register.
The control register basically tells you that a transmission is in progress,
when it's done, the status of the received ack, etc.
That should provide enough data to setup you control statemachine.
Note that the opencores i2c controller is a master only device.
Question 3: In the i2c_master_top.vhd module, the assign wb_dat_o
process (~line 188), why are the addresses 000 and 001 assigned
values as though a 32 bit data stream came in? I don't know if it's very
important, but it's very confusing to me why that happens.
[rih] I don't understand. The 'prer' register is a 16bit register, but
wb_dat_o is only 8bits.
Therefore two addresses (000 and 001) are used to return the hi and lo byte.
I'd like to say, this i2c code takes a while for an amateur (me) to figure
out, but it's very elegant code once you start to grasp it. Thumbs up
to Mr. H. Very nice.
[rih] Thanks :)
There's a learning curve for anything you use.
Obviously I have my own ideas on how to use a peripheral and how to write
code.
Which is reflected in this core. Some people may agree, others might not.
But the core works and is used by many people (and companies) around the
world, which seems to be a testimony for the stability of the code.
Richard
I'll definitely have more questions later, thanks in advance for
everyone's time.
----- Original Message -----
From: Richard Herveillerichard at h...>
To:
Date: Fri Mar 28 16:07:15 CET 2008
Subject: [oc] Integrate I2C core into FPGA
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
Get a hold of the Wisbone SoC Interconnect document.
It is posted on the opencores website.
Wishbone is a pretty straightforward interconnect.
Most of the names should be self explanatory.
The i2c master provided on opencores should do just fine what you
need.
However it is only an i2c interface. It requires a controller
(statemachine,
cpu, whatever) to program the i2c master.
Richard
-----Original Message-----
From: cores-bounces at opencores.org [mailto:cores-bounces at
opencores.org] On
Behalf Of dslaman0877 at yahoo.com
Sent: 28 March 2008 00:40
To: cores at opencores.org
Subject: Re: [oc] Integrate I2C core into FPGA
Guess was close, but off by a couple digits: PCA9564. I have the
data
sheet, and I would say I have an OK understanding of it's
operation.
Thank you very much for that explanation, it is very helpful. I've
only
been able to find one person that's even heard of the wishbone
protocol
and it ended there, he had only heard of it. But that explanation
helps
make sense out of the code. Even though it's not the same chip, the
link helps too.
----- Original Message -----
From: andrew mulcock
To:
Date: Wed Mar 26 21:16:17 CET 2008
Subject: [oc] Integrate I2C core into FPGA
http://www.ai.rug.nl/~pave/i2c/i2c_to_parallel_port_text.html#pcf8584
> Wishbone first.
> > Wishbone is a 'computer bus' inside the FPGA with master and > peripherals ( > slaves ). > > Think of an address bus and a data bus. On a PC the data would be
> bi
> directional, with tri state drivers on each peripheral. > As FPGA's don't support bi directional bus's the data bus is split
> into two
> one from master, one too master. > As FPGA's don't tend to support internal tri state bus's, then > 'and' gates > are used. > take the output of all the peripherals, and 'and' them together.
> The 'trick' is to make certain the output of all but the
> peripheral > you want is set at zero, > I guess you currently have a 'Philips' parallel to I2C chip, > PCF8584. which > is what you want to replace. > you might want to take a look here to get a handle on the chip
> your
> trying to replace. > > >
> -----Original Message-----
> From: cores-bounces at opencores.org [mailto:cores-bounces at > opencores.org] On > Behalf Of dslaman0877 at yahoo.com > Sent: 26 March 2008 18:12 > To: cores at opencores.org > Subject: [oc] Integrate I2C core into FPGA > I'm currently working on a senior project (EE undergrad) where one
> of
> the requirements is to replace an existing I2C chip with a coded
> version
> of the I2C loaded directly onto the FPGA. I really want to use the
> I2C
> core from this site written by Richard Herveille, but I'm really
> confused
> about how the whole wishbone thing works. > The system the I2C is interfaced with is very simple. Overall, the
> device is a camera. I have a KODAK board (imaging sensor)
connected
> to a board that contains all the electrical components (RAM,
FPGA:
> XCV300-4PQ240C in PQFP 240 pin package, USB DLP chip, I2C
chip)
> which connects to a computer via the USB port. Matlab owns the
> whole process, there are 2 files written that write the KODAK > registers > and the reads them (for verification) over the I2C chip. > I've had to reverse engineer the project, I was given a prototype,
> told
> to figure it out by building the whole thing from the ground up,
> and then
> make the changes per requirements. > Currently, there is a statemachine in the VHDL code that evenutally
> outputs received signals from the FPGA to the I2C chip. The
only
> pins
> hooked up as outputs of the FPGA to inputs of the I2C chip are: A0,
> A1,
> WT', RD' CE', and RST'. D0-D7 (8-bit data line) is hooked up to the > I2C > as bi-directional data. Finally, I have the SCL and SDA lines > hooked up > to the Kodak board. > My idea was to redefine the outputs of the FPGA as internal signals
> that > would map to the I2C core signals. I think that the
clock > everything is > running off of needs to be mapped to
the clock signal in the I2C > core as > well. I know I'm
asking for a whole lot of help here, but I'm > really >
running out of places to turn to. thanks >
_______________________________________________ >
http://www.opencores.org/mailman/listinfo/cores > No virus found
in this incoming message. > Checked by AVG. > Version:
7.5.519 / Virus Database: 269.22.0/1343 - Release Date: >
25/03/2008 > 19:17 > No virus found in this outgoing message.
> Checked by AVG. > Version: 7.5.519 / Virus Database:
269.22.0/1343 - Release Date: > 25/03/2008 > 19:17 > >
> _______________________________________________
http://www.opencores.org/mailman/listinfo/cores
|
|||
1/1