Hello, I integrated the i2c ocore IP(VHDL) in a design with other Wishbone IPhttp://www.armadeus.com/wiki/uploads/c/c5/Wishboneocore.png>and a irq manager core. The FPGA (spartan3) is connected to an ARM-processor (imx) with linux as operating system ( http://www.armadeus.com). With my design, I only can read/write in 16bits data bus mode (with sel=11). Then I write on register TXR and CR at the same time for example. Reading the VHDL IP code I found these address decode: ---------------------------------- RXR | SR | 11 TXR | CR | 10 | CTR | 01 PRERhi | PRERlo | 00 ---------------------------------- To test this core, I branched an accelerometer on i2c bus (address 0x1d) and I read/write on the same register (0x16). Then I wrote a simple proc driver that do : #unmask interrupt for i2c in interrupt manager: write 0x0002 in IRQ_MASK #Configure i2c speed prescaler (100kHz, FPGA clock is 96MHz) write 0x00bf in PRESCALER (address 00) #Enable core and enable interruption write 0x00c0 in CTR (address 01) #send start and address in write mode (address 0x1dhttp://www.opencores.org/forums.cgi/cores/attachments/20080408/546225f4/attachment.htm

The core never releases SDA and SCL at the same time. The order you specified sounds fine and it works on the 8bit interface. Are you sure you didn’t break anything when you modified the 8bit interface to a 16bit interface? Richard From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of Fabien Marteau Sent: 08 April 2008 11:41 To: cores at opencores.org Subject: [oc] i2c ocore linux driver. Hello, I integrated the i2c ocore IP(VHDL) in a design with other http://www.armadeus.com/wiki/uploads/c/c5/Wishboneocore.png> Wishbone IP and a irq manager core. The FPGA (spartan3) is connected to an ARM-processor (imx) with linux as operating system ( http://www.armadeus.com). With my design, I only can read/write in 16bits data bus mode (with sel=11). Then I write on register TXR and CR at the same time for example. Reading the VHDL IP code I found these address decode: ---------------------------------- RXR | SR | 11 TXR | CR | 10 | CTR | 01 PRERhi | PRERlo | 00 ---------------------------------- To test this core, I branched an accelerometer on i2c bus (address 0x1d) and I read/write on the same register (0x16). Then I wrote a simple proc driver that do : #unmask interrupt for i2c in interrupt manager: write 0x0002 in IRQ_MASK #Configure i2c speed prescaler (100kHz, FPGA clock is 96MHz) write 0x00bf in PRESCALER (address 00) #Enable core and enable interruption write 0x00c0 in CTR (address 01) #send start and address in write mode (address 0x1dhttp://www.opencores.org/forums.cgi/cores/attachments/20080409/053dbde6/attachment-0001.htm

Thanks for your quick response. I used this VHDL file : http://www.opencores.org/cvsweb.cgi/~checkout~/i2c/vhdl/Attic/wishbone_i2c_master.vhd?rev=1.1;content-type=text%2Fplain And I just changed this line : ADR_I : in unsigned(1 downto 0); -- lower address bits with ADR_I : in std_logic_vector(1 downto 0); -- lower address bits And I added some signals on process sensivity list: ocess(clk, nReset, state, dcnt, core_txd,core_cmd,go,start,read,core_ack,sr,ack_in,stop) [...] nxt_state_decoder : process (clk, nReset, state, cmd,txd,Din) [...] output_decoder: process (clk, nReset, state,SCLo,sSDA,Din) To synthetize with less warning. And I added these lines in my top component : SCL is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. The first warning is strange, because in VHDL txd *is* assigned. FabM 2008/4/9 Richard Herveille richard at herveille.net>:

>>>>> "FM" == Fabien Marteau fabien.marteau at armadeus.com> writes: Hi, FM> Is somebody has this problem, or do you think it is a wrong programming ? I haven't seen that issue, no. FM> I saw there is a linux driver for this core but, of course, without irq_mng FM> and with 8bit write. I will try to modify it to read/write in 16bits. That should just be a matter of tweaking oc_setreg / oc_getreg. -- Sorry about disclaimer - It's out of my control. Bye, Peter Korsgaard

So the interface remains 8bit, then how can you write 16bits? That doesn't work; you need to address the core as an 8bit peripheral. Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of Fabien Marteau Sent: 10 April 2008 09:50 To: Discussion list about free open source IP cores Subject: Re: *** PROBABLY SPAM *** RE: [oc] i2c ocore linux driver. Thanks for your quick response. I used this VHDL file : http://www.opencores.org/cvsweb.cgi/~checkout~/i2c/vhdl/Attic/wishbone_i2c_master.vhd?rev=1.1;content-type=text%2Fplain And I just changed this line : ADR_I : in unsigned(1 downto 0); -- lower address bits with ADR_I : in std_logic_vector(1 downto 0); -- lower address bits And I added some signals on process sensivity list: ocess(clk, nReset, state, dcnt, core_txd,core_cmd,go,start,read,core_ack,sr,ack_in,stop) [...] nxt_state_decoder : process (clk, nReset, state, cmd,txd,Din) [...] output_decoder: process (clk, nReset, state,SCLo,sSDA,Din) To synthetize with less warning. And I added these lines in my top component : SCL is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. The first warning is strange, because in VHDL txd *is* assigned. FabM 2008/4/9 Richard Herveille richard at herveille.net>: _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

Re WARNING:Xst:646 - Signal is assigned but never used Check the ise warnings, you'll probably find that the signal either has no used output, so is 'pruned' by the optimiser, or the sensitivity list is wrong, meaning the signal was not used in a equation and again optimised out. You really should have no sensitivity list warnings, if you do different tools can and do do different things, Oh and you might want to change the lines SCL cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of Fabien Marteau Sent: 10 April 2008 08:50 To: Discussion list about free open source IP cores Subject: Re: *** PROBABLY SPAM *** RE: [oc] i2c ocore linux driver. Thanks for your quick response. I used this VHDL file : http://www.opencores.org/cvsweb.cgi/~checkout~/i2c/vhdl/Attic/wishbone_i2c_m aster.vhd?rev=1.1;content-type=text%2Fplain And I just changed this line : ADR_I : in unsigned(1 downto 0); -- lower address bits with ADR_I : in std_logic_vector(1 downto 0); -- lower address bits And I added some signals on process sensivity list: ocess(clk, nReset, state, dcnt, core_txd,core_cmd,go,start,read,core_ack,sr,ack_in,stop) [...] nxt_state_decoder : process (clk, nReset, state, cmd,txd,Din) [...] output_decoder: process (clk, nReset, state,SCLo,sSDA,Din) To synthetize with less warning. And I added these lines in my top component : SCL is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. The first warning is strange, because in VHDL txd *is* assigned. FabM 2008/4/9 Richard Herveille richard at herveille.net>:
interface to a 16bit interface?

Behalf Of Fabien Marteau

a irq manager core.
operating system ( http://www.armadeus.com).
sel=11). Then I write on register TXR and CR at the same time for example.
Reading the VHDL

and I read/write on the same register (0x16). Then I wrote a simple proc
driver that do :

interrupt

switching to 0 at the same time. It's ok to read, the component return the
good value, but this can be a problem for some components.

irq_mng and with 8bit write. I will try to modify it to read/write in
16bits.
_______________________________________________ http://www.opencores.org/mailman/listinfo/cores No virus found in this incoming message. Checked by AVG. Version: 7.5.519 / Virus Database: 269.22.12/1373 - Release Date: 11/04/2008 09:17 No virus found in this outgoing message. Checked by AVG. Version: 7.5.519 / Virus Database: 269.22.12/1373 - Release Date: 11/04/2008 09:17

Oh and you might want to change the lines SCL cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of Fabien Marteau Sent: 10 April 2008 08:50 To: Discussion list about free open source IP cores Subject: Re: *** PROBABLY SPAM *** RE: [oc] i2c ocore linux driver. Thanks for your quick response. I used this VHDL file : http://www.opencores.org/cvsweb.cgi/~checkout~/i2c/vhdl/Attic/wishbone_i2c_m aster.vhd?rev=1.1;content-type=text%2Fplain And I just changed this line : ADR_I : in unsigned(1 downto 0); -- lower address bits with ADR_I : in std_logic_vector(1 downto 0); -- lower address bits And I added some signals on process sensivity list: ocess(clk, nReset, state, dcnt, core_txd,core_cmd,go,start,read,core_ack,sr,ack_in,stop) [...] nxt_state_decoder : process (clk, nReset, state, cmd,txd,Din) [...] output_decoder: process (clk, nReset, state,SCLo,sSDA,Din) To synthetize with less warning. And I added these lines in my top component : SCL is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. The first warning is strange, because in VHDL txd *is* assigned. FabM 2008/4/9 Richard Herveille richard at herveille.net>:
interface to a 16bit interface?

Behalf Of Fabien Marteau

a irq manager core.
operating system ( http://www.armadeus.com).
sel=11). Then I write on register TXR and CR at the same time for example.
Reading the VHDL

and I read/write on the same register (0x16). Then I wrote a simple proc
driver that do :

interrupt

switching to 0 at the same time. It's ok to read, the component return the
good value, but this can be a problem for some components.

irq_mng and with 8bit write. I will try to modify it to read/write in
16bits.
_______________________________________________ http://www.opencores.org/mailman/listinfo/cores No virus found in this incoming message. Checked by AVG. Version: 7.5.519 / Virus Database: 269.22.12/1373 - Release Date: 11/04/2008 09:17 No virus found in this outgoing message. Checked by AVG. Version: 7.5.519 / Virus Database: 269.22.12/1373 - Release Date: 11/04/2008 09:17 _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

I configured SEL pins on top component : SEL


I changed these lines, and I ve got the same result. Scope traces can be seen here : http://uuu.enseirb.fr/~marteau/ocore-i2c/i2cocore.html Thanks FabM On Sat, Apr 12, 2008 at 11:40 AM, Richard Herveille richard at herveille.net> wrote: -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20080414/ed93d228/attachment.htm

I configured SEL pins on top component : SEL
[rih] Right, but the i2c core is an 8bit core. Unless you got a bus switch that handles breaking up the 16bit access in 2 8bit accesses the MSBs will be ignored.
All accesses to the i2c core must be 8bit accesses.

Richard







I changed these lines, and I ve got the same result. Scope traces can be seen here : http://uuu.enseirb.fr/~marteau/ocore-i2c/i2cocore.html Thanks FabM On Sat, Apr 12, 2008 at 11:40 AM, Richard Herveille richard at herveille.net> wrote: Oh and you might want to change the lines SCL cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of Fabien Marteau Sent: 10 April 2008 08:50 To: Discussion list about free open source IP cores Subject: Re: *** PROBABLY SPAM *** RE: [oc] i2c ocore linux driver. Thanks for your quick response. I used this VHDL file : http://www.opencores.org/cvsweb.cgi/~checkout~/i2c/vhdl/Attic/wishbone_i2c_m http://www.opencores.org/cvsweb.cgi/%7Echeckout%7E/i2c/vhdl/Attic/wishbone_i2c_master.vhd?rev=1.1;content-type=text%2Fplain> aster.vhd?rev=1.1;content-type=text%2Fplain And I just changed this line : ADR_I : in unsigned(1 downto 0); -- lower address bits with ADR_I : in std_logic_vector(1 downto 0); -- lower address bits And I added some signals on process sensivity list: ocess(clk, nReset, state, dcnt, core_txd,core_cmd,go,start,read,core_ack,sr,ack_in,stop) [...] nxt_state_decoder : process (clk, nReset, state, cmd,txd,Din) [...] output_decoder: process (clk, nReset, state,SCLo,sSDA,Din) To synthetize with less warning. And I added these lines in my top component : SCL is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. The first warning is strange, because in VHDL txd *is* assigned. FabM 2008/4/9 Richard Herveille richard at herveille.net>:
interface to a 16bit interface?

Behalf Of Fabien Marteau

a irq manager core.
operating system ( http://www.armadeus.com).
sel=11). Then I write on register TXR and CR at the same time for example.
Reading the VHDL

and I read/write on the same register (0x16). Then I wrote a simple proc
driver that do :

interrupt

switching to 0 at the same time. It's ok to read, the component return the
good value, but this can be a problem for some components.

irq_mng and with 8bit write. I will try to modify it to read/write in
16bits.
_______________________________________________ http://www.opencores.org/mailman/listinfo/cores No virus found in this incoming message. Checked by AVG. Version: 7.5.519 / Virus Database: 269.22.12/1373 - Release Date: 11/04/2008 09:17 No virus found in this outgoing message. Checked by AVG. Version: 7.5.519 / Virus Database: 269.22.12/1373 - Release Date: 11/04/2008 09:17 _______________________________________________ http://www.opencores.org/mailman/listinfo/cores _______________________________________________ http://www.opencores.org/mailman/listinfo/cores -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20080415/446c1575/attachment.html

----- Original Message ----- From: Richard Herveillerichard at h...> To: Date: Fri Apr 11 09:52:01 CEST 2008 Subject: *** PROBABLY SPAM *** RE: [oc] i2c ocore linux driver. http://www.opencores.org/cvsweb.cgi/~checkout~/i2c/vhdl/Attic/wishb one_i2c_master.vhd?rev=1.1;content-type=text%2Fplain
address bits