Out of curiosity, was this thing synthesized on chip and tested, or was
this just a simulated design to help design the wishbone i2c master core?

The design was actually implemented in an EPLD. With some additional logic to display the temperature on some 7segment displays. Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of dslaman0877 at yahoo.com Sent: 10 April 2008 19:39 To: cores at opencores.org Subject: [oc] i2c.vhd and dallas statemachine Out of curiosity, was this thing synthesized on chip and tested, or was this just a simulated design to help design the wishbone i2c master core? _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

One more question regarding this, I'm just horseing around with this code now, but there is something fundamental that I can't decipher by looking at the i2c.vhd code. In the dallas test code, why are start conditions plus read/write plus the data byte all updated at the same time? Looking at the code for the i2c component, it looks like one command should be set at a time: like send a start, then send a read or write, etc. How does the code know how to take all those commands and perform the operations in the right order? I know you usually only answer questions regarding the master i2c core, but I want to try and understand this simpler version first. thanks. ----- Original Message ----- From: Richard Herveillerichard at h...> To: Date: Fri Apr 11 09:54:10 CEST 2008 Subject: [oc] i2c.vhd and dallas statemachine

What would be a logical order for an i2c command? Hmmmm .... start read/write stop?? That's exactly what the core does. The statemachine simply checks the start command bit first, then data transfer, then stop. Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of dslaman0877 at yahoo.com Sent: 21 April 2008 21:16 To: cores at opencores.org Subject: Re: [oc] i2c.vhd and dallas statemachine One more question regarding this, I'm just horseing around with this code now, but there is something fundamental that I can't decipher by looking at the i2c.vhd code. In the dallas test code, why are start conditions plus read/write plus the data byte all updated at the same time? Looking at the code for the i2c component, it looks like one command should be set at a time: like send a start, then send a read or write, etc. How does the code know how to take all those commands and perform the operations in the right order? I know you usually only answer questions regarding the master i2c core, but I want to try and understand this simpler version first. thanks. ----- Original Message ----- From: Richard Herveillerichard at h...> To: Date: Fri Apr 11 09:54:10 CEST 2008 Subject: [oc] i2c.vhd and dallas statemachine _______________________________________________ http://www.opencores.org/mailman/listinfo/cores